# US 12,218,131 B2 · Semiconductor device including gate separation region > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,131 B2 - Document ID: US12218131B2 - Status: Granted - Kind: B2 - Application number: 18/591,687 - Filed: 2024-02-29 - Published: 2024-06-20 - Granted: 2025-02-04 - Earliest claimed: 2018-04-26 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sun Ki Min - Web page: https://patentgrep.com/patent/US12218131B2 ## CPC - H10D 84/834: {comprising FinFETs} - H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)} - H10D 30/792: {comprising applied insulating layers, e.g. stress liners} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 64/517: {characterised by the conducting layers} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer. ## Claims ### Claim 1 A semiconductor device, comprising: a first active region and a second active region spaced apart from each other; an isolation region on side surfaces of the first and second active regions; a first gate structure overlapping the first active region and the isolation region; a second gate structure overlapping the second active region and the isolation region; and a gate separation region between the first gate structure and the second gate structure, wherein the first gate structure includes a first gate dielectric layer, a first gate electrode on the first gate dielectric layer and a first capping layer on the first gate electrode, wherein the second gate structure includes a second gate dielectric layer, a second gate electrode on the second gate dielectric layer and a second capping layer on the second gate electrode, wherein each of the first and second gate structures has a line shape or bar shape in a first direction, wherein the first gate structure and the second gate structure are spaced apart from each other in the first direction, wherein the first gate structure, the gate separation region and the second gate structure are sequentially arranged in the first direction, wherein a lower end of the gate separation region is at a lower level than lower surfaces of the first and second gate structures adjacent to the gate separation region, wherein the gate separation region includes: a lower insulating layer between the first gate electrode and the second gate electrode; and an upper insulating layer between the first capping layer and the second capping layer, wherein a material of the upper insulating layer is different from a material of the lower insulating layer, and wherein a lower surface of the gate separation region has a rounded shape. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the material of the upper insulating layer has a dielectric constant that is higher than a dielectric constant of the material of the lower insulating layer. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, wherein a maximum width in the first direction of the lower insulating layer is greater than a maximum width in the first direction of the upper insulating layer. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein a thickness in a vertical direction of the lower insulating layer is different from a thickness in the vertical direction of the upper insulating layer. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein a thickness in a vertical direction of the lower insulating layer is greater than a thickness in the vertical direction of the upper insulating layer. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first gate dielectric layer is between the first active region and the first gate electrode, between the isolation region and the first gate electrode, and between the lower insulating layer and the second gate electrode, and wherein the second gate dielectric layer is between the second active region and the second gate electrode, between the isolation region and the second gate electrode, and between the lower insulating layer and the second gate electrode. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, wherein a lower surface of the upper insulating layer contacts an upper surface of the lower insulating layer. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1, wherein the gate separation region further includes an insulating liner between the first capping layer and the upper insulating layer, and between the second capping layer and the upper insulating layer. ### Claim 9 (depends on 8) The semiconductor device as claimed in claim 8, wherein the material of the upper insulating layer has a dielectric constant that is higher than a dielectric constant of the material of the lower insulating layer, and wherein a material of the insulating liner has a dielectric constant that is higher than the dielectric constant of the material of the lower insulating layer. ### Claim 10 (depends on 9) The semiconductor device as claimed in claim 9, wherein the dielectric constant of the material of the upper insulating layer is higher than the dielectric constant of the material of the insulating liner. ### Claim 11 (depends on 8) The semiconductor device as claimed in claim 8, wherein a lower surface of the upper insulating layer contacts an upper surface of the lower insulating layer. ### Claim 12 (depends on 1) The semiconductor device as claimed in claim 1, wherein the gate separation region further includes an insulating liner between the first capping layer and the upper insulating layer, between the second capping layer and the upper insulating layer, between the first gate electrode and the lower insulating layer, between the second gate electrode and the lower insulating layer, and between the isolation region and the lower insulating layer. ### Claim 13 (depends on 1) The semiconductor device as claimed in claim 1, wherein the gate separation region further includes an insulating liner between the first capping layer and the upper insulating layer, between the second capping layer and the upper insulating layer, and between the upper insulating layer and the lower insulating layer. ### Claim 14 A semiconductor device, comprising: a first source/drain region and a second source/drain region spaced apart from each other; first active layers between the first source/drain region and the second source/drain region; a third source/drain region and a fourth source/drain region spaced apart from each other; second active layers between the third source/drain region and the fourth source/drain region; a first gate structure overlapping the first active layers and extending in a first direction; a second gate structure overlapping the second active layers and extending in the first direction; and a gate separation region between the first gate structure and the second gate structure, wherein the first active layers are spaced apart from each other in a vertical direction, wherein the second active layers are spaced apart from each other in the vertical direction, wherein the first gate structure covers an upper surface, a side surface and a bottom surface of each of the first active layers, wherein the second gate structure covers an upper surface, a side surface and a bottom surface of each of the second active layers, wherein the first gate structure includes a first gate dielectric layer, a first gate electrode on the first gate dielectric layer and a first capping layer on the first gate electrode, wherein the second gate structure includes a second gate dielectric layer, a second gate electrode on the second gate dielectric layer and a second capping layer on the second gate electrode, wherein the gate separation region includes: a lower insulating layer between the first gate electrode and the second gate electrode; and an upper insulating layer between the first capping layer and the second capping layer, and wherein a material of the upper insulating layer has a dielectric constant that is higher than a dielectric constant of a material of the lower insulating layer. ### Claim 15 (depends on 14) The semiconductor device as claimed in claim 14, wherein the dielectric constant of the material of the lower insulating layer is lower than a dielectric constant of a silicon nitride. ### Claim 16 (depends on 14) The semiconductor device as claimed in claim 14, wherein the gate separation region further includes an insulating liner contacting at least one of the upper insulating layer and the lower insulating layer. ### Claim 17 (depends on 16) The semiconductor device as claimed in claim 16, wherein a material of the insulating liner is different from the material of the upper insulating layer and the material of the lower insulating layer. ### Claim 18 (depends on 16) The semiconductor device as claimed in claim 16, wherein the dielectric constant of the material of the upper insulating layer is higher than a dielectric constant of a material of the insulating liner. ### Claim 19 (depends on 18) The semiconductor device as claimed in claim 18, wherein the dielectric constant of a material of the insulating liner is higher than the dielectric constant of a material of the lower insulating layer. ### Claim 20 (depends on 16) The semiconductor device as claimed in claim 16, wherein insulating liner is between the first capping layer and the upper insulating layer, between the second capping layer and the upper insulating layer, between the first gate electrode and the lower insulating layer, and between the second gate electrode and the lower insulating layer.