# US 12,218,130 B2 · Semiconductor structure cutting process and structures formed thereby

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- Number: US 12,218,130 B2
- Document ID: US12218130B2
- Status: Granted
- Kind: B2
- Application number: 18/526,290
- Filed: 2023-12-01
- Published: 2024-04-04
- Granted: 2025-02-04
- Earliest claimed: 2017-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Chang Hung; Chia-Jen Chen; Ming-Ching Chang; Shu-Yuan Ku; Yi-Hsuan Hsiao; I-Wei Yang
- Web page: https://patentgrep.com/patent/US12218130B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 64/679: {comprising air gaps}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/40: of conductive or resistive materials
- H10P 50/267: {using plasmas}
- H10P 50/283: {by chemical means}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 52/403: {of conductive or resistive materials}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

## Claims

### Claim 1

A method comprising:
forming a first gate structure over a first active area and a second active area on a substrate, a dielectric layer being disposed along opposing sides of the first gate structure;
performing a first etch process to form a first recess in the first gate structure and the dielectric layer;
performing a second etch process to laterally widen the first recess, wherein after the second etch process, a width of the first recess in the first gate structure is wider along a first line parallel to a longitudinal axis of the first gate structure than a width of the first recess in the dielectric layer along a second line parallel to the first line; and
filling the first recess with a dielectric material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first etch process comprises an anisotropic etch process.

### Claim 3 (depends on 2)

The method of claim 2, wherein the anisotropic etch process comprises one or more cycles, wherein each cycle comprises:
a passivation deposition;
a passivation break through;
a gate etching; and
a flash etching.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second etch process comprises an isotropic etch process.

### Claim 5 (depends on 1)

The method of claim 1, further comprising, prior to performing the first etch process, forming a mask layer with a mask opening.

### Claim 6 (depends on 5)

The method of claim 5, wherein the mask opening has a first width over the first gate structure and a second width over the dielectric layer, wherein the first width is different than the second width.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first width is greater than the second width.

### Claim 8 (depends on 5)

The method of claim 5, wherein the mask opening has a same width over the first gate structure and the dielectric layer.

### Claim 9

A method comprising:
forming a first gate structure over a first active area, a dielectric layer being disposed along opposing sides of the first gate structure;
performing an anisotropic etch process to form a first recess, the first recess exposing sidewalls of the first gate structure and the dielectric layer;
after performing the anisotropic etch process, performing an isotropic etch process to recess sidewalls of the first gate structure and the dielectric layer thereby forming a second recess, wherein the isotropic etch process etches the first gate structure at a faster rate than the dielectric layer; and
forming a dielectric material in the second recess.

### Claim 10 (depends on 9)

The method of claim 9, wherein the anisotropic etch process comprises one or more cycles of a passivation deposition, a passivation break through, a gate etching, and a flash etching.

### Claim 11 (depends on 9)

The method of claim 9, wherein the second recess completely separates the first gate structure into a second gate structure and a third gate structure.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first recess completely separates the first gate structure into a second gate structure and a third gate structure.

### Claim 13 (depends on 9)

The method of claim 9, wherein a distance between the first active area and the dielectric material is in a range between 5 nm and 15 nm.

### Claim 14 (depends on 9)

The method of claim 9, wherein the first gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer, wherein the dielectric material directly contacts the gate dielectric layer and the gate electrode.

### Claim 15

A method comprising:
forming a first conductive line structure and a second conductive line structure over a substrate, the first conductive line structure and the second conductive line structure being separated by a first interlayer dielectric;
performing a first etch process and a second etch process different than the first etch process to form a cut opening, the cut opening separating the first conductive line structure into a first gate structure and a second gate structure, the cut opening separating the second conductive line structure into a third gate structure and a fourth gate structure, the cut opening having a first width, a second width, and a third width, the first width being a largest width of the cut opening between the first gate structure and the second gate structure, the second width of the cut opening being a largest width of the cut opening in a first dielectric layer between the first conductive line structure and the second conductive line structure, the third width being a largest width of the cut opening between the third gate structure and the fourth gate structure, wherein the first width and the third width is greater than the second width; and
forming a first dielectric structure in the cut opening.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first etch process forms a first opening through the first conductive line structure.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second etch process widens the first opening to form the cut opening.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the first dielectric structure comprises forming a first dielectric layer in the cut opening and a second dielectric layer over the first dielectric layer in the cut opening, further comprising forming second interlayer dielectric over the first interlayer dielectric and the first dielectric structure, wherein a first void exists between the second interlayer dielectric and the second dielectric layer in the cut opening.

### Claim 19 (depends on 18)

The method of claim 18, wherein a second void exists between the second interlayer dielectric and the second dielectric layer in the cut opening, wherein the first void is separated from the first void.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first void is between the first gate structure and the second gate structure, wherein the second void is between the third gate structure and the fourth gate structure.