# US 12,218,127 B2 · Electrostatic discharge circuit having stable discharging mechanism > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,127 B2 - Document ID: US12218127B2 - Status: Granted - Kind: B2 - Application number: 17/994,422 - Filed: 2022-11-28 - Published: 2023-06-01 - Granted: 2025-02-04 - Earliest claimed: 2021-11-30 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corporation - Inventors: Chung-Yu Huang - Web page: https://patentgrep.com/patent/US12218127B2 ## CPC - H10D 89/811: {using FETs as protective elements} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H02M 7/539: with automatic control of output wave form or frequency (H02M7/5375 - H02M7/5387 take precedence) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal. ## Claims ### Claim 1 A circuit for discharging electrostatic, comprising: a voltage-dividing circuit electrically coupled to a voltage input terminal that is configured to receive a power signal, so as to generate a detection signal at a voltage-dividing terminal; a first inverter configured to receive and invert the detection signal to output an inverted detection signal; a voltage boosting circuit comprising: a first PMOS circuit and a first NMOS circuit electrically coupled in series between the voltage input terminal and a ground terminal through a first terminal, wherein the first PMOS circuit comprises a first PMOS control terminal electrically coupled to a second terminal and the first NMOS circuit comprises a first NMOS control terminal configured to receive the inverted detection signal; and a second NMOS circuit electrically coupled between the second terminal and the ground terminal and comprising a second NMOS control terminal configured to receive the detection signal; a first circuit comprising a resistive circuit for providing resistance that is electrically coupled between the voltage input terminal and a control terminal and a capacitive circuit for providing capacitance that is electrically coupled between the control terminal and a ground terminal, wherein the control terminal is electrically coupled to the second terminal; a second inverter electrically coupled between the voltage input terminal and the ground terminal and configured to receive and invert an inverted boosted detection signal from the control terminal to output a boosted detection signal; and an electrostatic discharge (ESD) transistor electrically coupled between the voltage input terminal and the ground terminal and configured to be controlled by the boosted detection signal for performing discharging on the voltage input terminal when being controlled to be turned on by the boosted detection signal; wherein under an ordinary operation mode that a voltage at the voltage input terminal does not exceed a predetermined level, the detection signal is at a low state level, the inverted detection signal is at a high state level, the first NMOS circuit is turned on and the first PMOS circuit and the second NMOS circuit are turned off, the inverted boosted detection signal is at the high state level and the boosted detection signal is at the low state level such that the electrostatic discharge transistor is turned off; and wherein under a discharging mode that a voltage at the voltage input terminal exceeds a predetermined level due to a reception of an electrostatic input, the detection signal is at a high state level, the inverted detection signal is at a low state level, the first NMOS circuit is turned off and the first PMOS circuit and the second NMOS circuit are turned on, the inverted boosted detection signal is at the low state level and the boosted detection signal is at the high state level such that the electrostatic discharge transistor is turned on. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first inverter operates according to a first voltage and the voltage boosting circuit, the second inverter and the electrostatic discharge transistor operate according to a second voltage generated according to the power signal, wherein the first voltage is smaller than the second voltage, the first voltage being 0.9, 1.2 or 1.8 volts and the second voltage being 3.3 volts. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the second voltage is generated according to the power signal and the first voltage is generated according to another independent voltage source. ### Claim 4 (depends on 2) The circuit of claim 2, wherein the second voltage is generated according to the power signal and the first voltage is generated by a divided power signal divided from the power signal. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the voltage-dividing circuit comprises a first resistive circuit and a second resistive circuit electrically coupled in series between the voltage input terminal and the ground terminal through the voltage-dividing terminal, wherein each of the first resistive circuit and the second resistive circuit comprises a resistor, a diode, a diode-connected transistor or a combination thereof. ### Claim 6 (depends on 1) The circuit of claim 1, wherein each of the first NMOS circuit and the second NMOS circuit comprises a first N-type transistor and a second N-type transistor electrically coupled in series, wherein the first N-type transistor is an I/O device and the second N-type transistor is a core device. ### Claim 7 (depends on 1) The circuit of claim 1, further comprising a second P-type transistor circuit electrically coupled between the voltage input terminal and the second terminal and so as to be electrically coupled to the second NMOS circuit in series, and the second P-type transistor circuit comprises a second P-type transistor control terminal electrically coupled to the first terminal. ### Claim 8 (depends on 1) The circuit of claim 1, wherein a time constant of the first circuit determines a high frequency response time of the circuit, the voltage-dividing circuit and the first inverter determines a low frequency response time of the circuit. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the first circuit is a RC circuit, the resistive circuit comprises a resistor and the capacitive circuit comprises a capacitor.