# US 12,218,125 B2 · Electro-static discharge protection structure and chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,125 B2 - Document ID: US12218125B2 - Status: Granted - Kind: B2 - Application number: 17/658,293 - Filed: 2022-04-07 - Published: 2023-01-19 - Granted: 2025-02-04 - Earliest claimed: 2021-07-14 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Qian Xu - Web page: https://patentgrep.com/patent/US12218125B2 ## CPC - H10D 89/711: {using bipolar transistors as protective elements} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 89/611: {using diodes as protective elements} - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D 8/411: {PN diodes having planar bodies} - H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 89/911: {using passive elements as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart. ## Claims ### Claim 1 An electro-static discharge protection structure, comprising: a semiconductor substrate; a first P-type well, located in the semiconductor substrate; a first N-type well, located in the semiconductor substrate; a first N-type doped portion, located in the first N-type well; a first P-type doped portion, located in the first N-type well, and spaced apart from the first N-type doped portion; a second N-type doped portion, located in the first P-type well; a second P-type doped portion, located in the first P-type well, and spaced apart from the second N-type doped portion; a third doped well, located in the semiconductor substrate; a third P-type doped portion, located in the third doped well; and a third N-type doped portions, located in the third doped well, and spaced apart from the third P-type doped portion, wherein the second N-type doped portion, the second P-type doped portion and the third N-type doped portion are electrically connected; and the first N-type doped portion is electrically connected to the third P-type doped portion. ### Claim 2 (depends on 1) The electro-static discharge protection structure according to claim 1, comprising a plurality of the third doped wells, a plurality of the third P-type doped portions and a plurality of the third N-type doped portions, wherein the plurality of the third doped wells are spaced apart, the plurality of the third P-type doped portions are provided in one-to-one correspondence with the plurality of the third doped wells, and the plurality of the third N-type doped portions are provided in one-to-one correspondence with the plurality of the third doped wells; the first N-type doped portion is electrically connected to any one of the plurality of the third P-type doped portions; the plurality of the third doped wells are sequentially connected in series through the third P-type doped portions and the third N-type doped portions therein, and in two adjacent connected third doped wells, the third P-type doped portion and the third N-type doped portion in different third doped wells are electrically connected; and the plurality of the third doped wells comprise a tail third doped well, the tail third doped well is connected to the first N-type doped portion through the other of the plurality of the third doped wells, and the second N-type doped portion and the second P-type doped portion are electrically connected to the third N-type doped portion in the tail third doped well. ### Claim 3 (depends on 2) The electro-static discharge protection structure according to claim 2, wherein there are two third doped wells. ### Claim 4 (depends on 2) The electro-static discharge protection structure according to claim 2, wherein the third doped well is located on a side of the first N-type well away from the first P-type well, the first P-type well, the first N-type well and the plurality of the third doped wells are sequentially arranged in a first direction, and the first direction is parallel to a plane of the semiconductor substrate. ### Claim 5 (depends on 4) The electro-static discharge protection structure according to claim 4, wherein the first P-type doped portion is located on a side of the first N-type doped portion close to the first P-type well, and the second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well; and in a same third doped well, the third N-type doped portion is located on a side of the third P-type doped portion away from the first N-type well, and in two adjacent third doped wells, adjacent third N-type doped portion and third P-type doped portion are electrically connected. ### Claim 6 (depends on 2) The electro-static discharge protection structure according to claim 2, wherein the third doped well is a P-type doped well or an N-type doped well. ### Claim 7 (depends on 2) The electro-static discharge protection structure according to claim 2, wherein the semiconductor substrate is a P-type semiconductor substrate. ### Claim 8 (depends on 7) The electro-static discharge protection structure according to claim 7, wherein the third doped well is a P-type well, and the electro-static discharge protection structure further comprises: an N-type deep well, located in the semiconductor substrate, the first P-type well, the first N-type well and the third doped well being located in the N-type deep well. ### Claim 9 (depends on 8) The electro-static discharge protection structure according to claim 8, further comprising: a fourth N-type doped portion, located in the N-type deep well, and connected to a power supply terminal. ### Claim 10 (depends on 9) The electro-static discharge protection structure according to claim 9, comprising two fourth N-type doped portions, wherein one of the fourth N-type doped portions, the first P-type well, the first N-type well, the plurality of the third doped wells and the other of the fourth N-type doped portions are sequentially arranged in a first direction, and the first direction is parallel to a plane of the semiconductor substrate. ### Claim 11 (depends on 8) The electro-static discharge protection structure according to claim 8, further comprising: a fourth P-type doped portion, located in the semiconductor substrate, spaced apart from the N-type deep well, and connected to a ground terminal. ### Claim 12 (depends on 11) The electro-static discharge protection structure according to claim 11, comprising two fourth P-type doped portions, wherein the two fourth P-type doped portions are located on two sides of the N-type deep well respectively; and one of the fourth P-type doped portions, the N-type deep well and the other of the fourth P-type doped portions are sequentially arranged in a first direction, and the first direction is parallel to a plane of the semiconductor substrate. ### Claim 13 (depends on 1) The electro-static discharge protection structure according to claim 1, wherein the second N-type doped portion, the second P-type doped portion and the third N-type doped portion are electrically connected through a conductive wire; and the first N-type doped portion is electrically connected to the third P-type doped portion through a conductive wire. ### Claim 14 (depends on 1) A chip, comprising the electro-static discharge protection structure according to claim 1. ### Claim 15 (depends on 14) The chip according to claim 14, wherein the second N-type doped portion in the electro-static discharge protection structure forms a first signal terminal of the electro-static discharge protection structure, and the first P-type doped portion in the electro-static discharge protection structure forms a second signal terminal of the electro-static discharge protection structure; and the chip comprises a power supply terminal, a ground terminal and a signal transmission terminal, the chip comprises a plurality of the electro-static discharge protection structures, and the plurality of the electro-static discharge protection structures comprise: a first electro-static discharge protection structure, comprising a first signal terminal connected to the power supply terminal, and a second signal terminal connected to the signal transmission terminal; a second electro-static discharge protection structure, comprising a first signal terminal connected to the signal transmission terminal, and a second signal terminal connected to the ground terminal; and a third electro-static discharge protection structure, comprising a first signal terminal connected to the ground terminal, and a second signal terminal connected to the power supply terminal.