# US 12,218,123 B2 · Chip parts > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,123 B2 - Document ID: US12218123B2 - Status: Granted - Kind: B2 - Application number: 17/948,929 - Filed: 2022-09-20 - Published: 2023-03-30 - Granted: 2025-02-04 - Earliest claimed: 2021-09-29 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Keisuke Fukae - Web page: https://patentgrep.com/patent/US12218123B2 ## CPC - H10D 1/692: {Electrodes} - H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] - H01G 4/008: Selection of materials - H01G 4/224: Housing; Encapsulation - H01G 4/228: Terminals - H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} - H01G 4/385: {Single unit multiple capacitors, e.g. dual capacitor in one coil} - H01G 4/40: Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations - H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 64/01: Manufacture or treatment - H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film. ## Claims ### Claim 1 A chip part, comprising: a substrate, having a first main surface and a second main surface opposite to the first main surface; a first external electrode and a second external electrode, disposed on the first main surface of the substrate and separated from each other; a capacitor portion, disposed on the first main surface of the substrate when viewed from a plan view and along a normal direction of the first main surface, wherein the capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on the first main surface, and the capacitor portion is disposed at least between the first external electrode and the second external electrode; a lower electrode, including: a first body portion, disposed along top and side surfaces of the plurality of wall portions; and a first peripheral portion, integrally drawn out around the capacitor portion from the first body portion; a capacitive film, including: a second body portion, disposed on the lower electrode, along the top and side surfaces of the plurality of wall portions and within the capacitor portion; and a second peripheral portion, integrally drawn out from the second body portion to the first peripheral portion; an upper electrode, disposed on the capacitive film; a first electrode film, electrically connecting the first external electrode to the lower electrode; and a second electrode film, electrically connecting the second external electrode to the upper electrode, wherein the first peripheral portion and the second peripheral portion are drawn out of an edge of the upper electrode in the plan view, and have a common edge located further out of the edge of the upper electrode, the plurality of wall portions are formed of a plurality of pillar units, each of the plurality of pillar units includes a central portion and three protruding portions extending from the central portion to three different directions in the plan view, and the plurality of wall portions are formed by connecting the three protruding portions of adjacent pillar units. ### Claim 2 (depends on 1) The chip part of claim 1, wherein the second peripheral portion of the capacitive film is formed in an annular shape and surrounds the capacitor portion in the plan view. ### Claim 3 (depends on 1) The chip part of claim 1, wherein the first electrode film, in the plan view, includes a lower contact portion formed as an annular shape and surrounding the capacitor portion, partially open on one side of the second external electrode and connected to the first peripheral portion of the lower electrode, and the second electrode film includes an upper contact portion connected to the upper electrode in an inner region of the lower contact portion. ### Claim 4 (depends on 1) The chip part of claim 1, wherein a functional component other than a capacitor is disposed on the first main surface of the semiconductor substrate and in a region overlapping with at least one of the first external electrode and the second external electrode in the plan view, and the functional component is electrically connected to the first external electrode and the second electrode as two terminals. ### Claim 5 (depends on 4) The chip part of claim 4, wherein the substrate includes a semiconductor substrate, and the functional component includes a diode having: a base region of a first conductivity type and formed on the first main surface of the semiconductor substrate; and an impurity region of a second conductivity type and formed in the base region. ### Claim 6 (depends on 5) The chip part of claim 5, wherein the diode includes: a first diode overlapping the first external electrode in the plan view; and a second diode overlapping the second external electrode in the plan view, wherein the first diode and the second diode form a bidirectional diode connected by the base region. ### Claim 7 (depends on 4) The chip part of claim 4, wherein the capacitor portion includes: a first overlapping portion, overlapping the first external electrode in the plan view; a second overlapping portion, overlapping the second external electrode in the plan view; and a center portion, disposed between the first external electrode and the second external electrode, wherein the functional component is disposed at a position away from the capacitor portion in a direction opposite to the first external electrode and the second external electrode. ### Claim 8 (depends on 1) The chip part of claim 1, wherein the substrate includes a semiconductor substrate formed as a quadrilateral first conductivity type semiconductor substrate surrounding the first main surface in the plan view, the quadrilateral first conductivity type semiconductor substrate having a pair of a first side surface and a second side surface facing each other and a pair of a third side surface and a fourth side surface facing each other, the first external electrode is disposed on the first side surface, the second external electrode is disposed on the second side surface, the first electrode film includes a lower contact portion connected to the first peripheral portion in a lower region of the first external electrode, the second electrode film includes an upper contact portion connected to the upper electrode, the chip part includes: a first diode, including an impurity region of a second conductivity type and formed in the semiconductor substrate between the lower contact portion and the first side surface in the plan view; and a second diode, including an impurity region of the second conductivity type and formed in the semiconductor substrate between the upper contact portion and the second side surface in the plan view, the first electrode film includes a first diode contact portion connected to the first diode, and the second electrode film includes a second diode contact portion connected to the second diode. ### Claim 9 (depends on 8) The chip part of claim 8, wherein the first diode includes a plurality of first diodes arranged along the first side surface of the semiconductor substrate. ### Claim 10 (depends on 8) The chip part of claim 8, wherein the second diode includes a plurality of second diodes arranged along the second side surface of the semiconductor substrate. ### Claim 11 (depends on 8) The chip part of claim 8, wherein the first external electrode forms a rectangle having a lengthwise direction along a direction of the first side surface and having a first long side, a second long side, a first short side and a second short side in the plan view, the first long side is a long side close to the first side surface and an opposite long side is the second long side, and the first diode is disposed overlapping a first outer peripheral edge portion along the first long side of the first external electrode. ### Claim 12 (depends on 11) The chip part of claim 11, wherein the second external electrode forms a rectangle having a lengthwise direction along a direction of the second side surface of the semiconductor substrate and having a third long side, a fourth long side, a third short side and a fourth short side in the plan view, the third long side is a long side close to the second side surface and an opposite long side is the fourth long side, and the second diode is disposed overlapping a second outer peripheral edge portion along the third long side of the second external electrode. ### Claim 13 (depends on 12) The chip part of claim 12, wherein the first external electrode includes a first inner peripheral portion along the second long side and on a side opposite to the first outer peripheral portion, the second external electrode includes a second inner peripheral portion along the fourth long side and on a side opposite to the second outer peripheral portion, and the capacitor portion includes the first peripheral portion overlapping the first inner peripheral portion and the second peripheral portion overlapping the second inner peripheral portion in the plan view. ### Claim 14 (depends on 8) The chip part of claim 8, wherein the first electrode film includes: a first base portion, disposed below the first external electrode and including the first diode contact portion; and a pair of first extending portions, branched and extending from the first base portion along two sides of the capacitor portion in directions of the third side surface and the fourth side surface. ### Claim 15 (depends on 14) The chip part of claim 14, wherein the second electrode film includes: a second base portion, disposed below the second external electrode and including the second diode contact portion; and a second extending portion, extending from the second base portion to a region between the pair of first extending portions and including the upper contact portion. ### Claim 16 (depends on 14) The chip part of claim 14, wherein the lower contact portion includes: a pair of strip-shaped first lower contact portions, disposed on each of the pair of first extending portions, and extending along the third side surface and the fourth side surface; and a strip-shaped second lower contact portion, extending at the first base portion along the first side surface. ### Claim 17 (depends on 16) The chip part of claim 16, wherein the pair of strip-shaped first lower contact portions are integrally formed with the strip-shaped second lower contact portion, and continuously extend from one end portion and another end portion in a lengthwise direction of the second lower contact portion toward the second external electrode. ### Claim 18 (depends on 8) The chip part of claim 8, wherein the upper contact portion is disposed to avoid a region overlapping with the first external electrode in the plan view. ### Claim 19 (depends on 1) The chip part of claim 1, wherein the capacitor portion, in the plan view, includes: a first capacitor portion, including the plurality of wall portions having the lengthwise direction as a first lengthwise direction; and a second capacitor portion, including the plurality of wall portions having the lengthwise direction as a second lengthwise direction across the first lengthwise direction. ### Claim 20 (depends on 19) The chip part of claim 19, wherein the first lengthwise direction and the second lengthwise direction are orthogonal to each other, and the chip part includes the first capacitor portion and the second capacitor portion disposed adjacent to each other.