# US 12,218,121 B2 · Semiconductor devices having improved layout designs, and methods of designing and fabricating the same

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- Number: US 12,218,121 B2
- Document ID: US12218121B2
- Status: Granted
- Kind: B2
- Application number: 17/373,510
- Filed: 2021-07-12
- Published: 2022-06-16
- Granted: 2025-02-04
- Earliest claimed: 2020-12-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jung Ho Do; Sanghoon Baek
- Web page: https://patentgrep.com/patent/US12218121B2

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10D 84/853: {comprising FinFETs}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2117/12: Sizing, e.g. of transistors or gates
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/975: {Wiring regions or routing}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

## Claims

### Claim 1

A semiconductor device including a first cell region, comprising:
an active pattern extending in a first direction, inside the first cell region;
a gate electrode extending in a second direction intersecting the first direction, inside the first cell region;
a source/drain contact connected to a source/drain region of the active pattern, on one side of the gate electrode; and
a first wiring pattern extending in the first direction and connected to one of the gate electrode and the source/drain contact;
wherein a part of the first wiring pattern protrudes from a boundary of the first cell region, and wherein a length of the first wiring pattern extending in the first direction is two gate pitches or less.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the length of the first wiring pattern extending in the first direction is 0.5 gate pitch or more and 1.5 gate pitches or less.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first cell region includes a plurality of routing tracks arranged along the second direction, and wherein the first wiring pattern is placed in one of the plurality of routing tracks.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising:
a second wiring pattern extending in the first direction and connected to the other of the gate electrode and the source/drain contact; and
wherein the second wiring pattern is placed in the other of the plurality of routing tracks.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the number of the plurality of routing tracks is in a range from one to three tracks.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first power supply wiring and a second power supply wiring extending side by side in the first direction; and
wherein the first wiring pattern is interposed between the first power supply wiring and the second power supply wiring.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first wiring pattern, the first power supply wiring, and the second power supply wiring are placed at the same routing level as each other.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a routing wiring extending in the second direction and connected to the first wiring pattern; and
wherein the routing wiring is placed at a routing level higher than the first wiring pattern.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the part of the first wiring pattern protrudes from the boundary of the first cell region extending in the second direction; and wherein a part of the second wiring pattern protrudes from the boundary of the first cell region extending in the first direction.

### Claim 10

A semiconductor device which includes a first cell region and a second cell region adjacent to each other and arranged along a first direction, the semiconductor device comprising:
a substrate;
a first cell separation pattern which extends in a second direction intersecting the first direction to separate the first cell region and the second cell region, on the substrate;
an active pattern extending in the first direction, on the substrate;
a first gate electrode, which extends in the second direction and is spaced apart from the first cell separation pattern by one gate pitch, on the substrate in the first cell region;
a first source/drain contact connected to a source/drain region of the active pattern of the first cell region, on one side of the first gate electrode; and
a first wiring pattern, which extends in the first direction over the first cell region and the second cell region, and is connected to one of the first gate electrode and the first source/drain contact; and
wherein a length of the first wiring pattern extending in the first direction is two gate pitches or less.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising:
a second gate electrode extending in the second direction, on the substrate in the second cell region;
a second source/drain contact connected to a source/drain region of the active pattern of the second cell region, on one side of the second gate electrode; and
a second wiring pattern that is spaced apart from the first cell separation pattern, extends in the first direction, and is connected to one of the second gate electrode and the second source/drain contact.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first wiring pattern and the second wiring pattern are arranged along the first direction and placed at the same routing level as each other.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a spaced distance of the second wiring pattern from the first cell separation pattern is 0.5 times a gate pitch or more.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the first cell region includes a plurality of first routing wirings including the first wiring pattern and placed at the same routing level as each other; and wherein the number of the first routing wirings arranged along the second direction among the plurality of the first routing wirings is three or less.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising:
a second cell separation pattern which extends in the second direction and is spaced apart from the first cell separation pattern by one gate pitch; and
wherein the second cell region is a filler cell region interposed between the first cell separation pattern and the second cell separation pattern.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the active pattern includes a fin-type pattern protruding from an upper surface of the substrate.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein the active pattern includes a plurality of wire patterns spaced apart from each other on the substrate.

### Claim 18

A layout design method for a semiconductor device, the method comprising:
providing a first cell region; and
providing a second cell region arranged adjacent to the first cell region along a first direction;
wherein the first cell region includes:
a gate electrode extending in a second direction intersecting the first direction;
a source/drain contact connected to a source/drain region of the first cell region, on one side of the gate electrode; and
a first wiring pattern which extends in the first direction over the first cell region and the second cell region, and is connected to one of the gate electrode and the source/drain contact.

### Claim 19 (depends on 18)

The layout design method for the semiconductor device of claim 18, wherein a length of the first wiring pattern extending in the first direction is two gate pitches or less.

### Claim 20 (depends on 18)

The layout design method for the semiconductor device of claim 18,
wherein the second cell region includes:
a second gate electrode extending in the second direction;
a second source/drain contact connected to a source/drain region of the second cell region, on one side of the second gate electrode, and
a second wiring pattern which extends in the first direction, is spaced apart from the first wiring pattern in the first direction, and is connected to one of the second gate electrode and the second source/drain contact; and
wherein the first wiring pattern and the second wiring pattern are placed at the same routing level as each other.