# US 12,218,108 B2 · Package and manufacturing method thereof

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- Number: US 12,218,108 B2
- Document ID: US12218108B2
- Status: Granted
- Kind: B2
- Application number: 18/586,549
- Filed: 2024-02-26
- Published: 2024-06-20
- Granted: 2025-02-04
- Earliest claimed: 2020-02-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsien-Wei Chen; Jie Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US12218108B2

## CPC

- H10W 90/00: Package configurations
- H10D 1/692: {Electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/251: {Materials}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 80/016: {Cleaning}
- H10W 80/041: {Thermally treating}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A package includes a first die, a second die, and an encapsulant. The first die includes a first capacitor. The second die includes a second capacitor. The second die is stacked on the first die. The first capacitor is spatially separated from the second capacitor. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.

## Claims

### Claim 1

A package, comprising:
a first die comprising a first capacitor;
a second die comprising a second capacitor, wherein the second die is stacked on the first die, the first capacitor is spatially separated from the second capacitor, and the first capacitor is electrically connected to the second capacitor; and
an encapsulant laterally encapsulating the second die.

### Claim 2 (depends on 1)

The package of claim 1, wherein the first die further comprises:
a first interconnection structure, wherein the first capacitor is embedded in the first interconnection structure;
a first bonding layer disposed over the first interconnection structure;
a passivation layer sandwiched between the first interconnection structure and the first bonding layer;
conductive pads embedded in the passivation layer; and
bonding vias penetrating through the passivation layer to connect the first bonding layer and the first capacitor.

### Claim 3 (depends on 2)

The package of claim 2, wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, one of the bonding vias is directly in contact with the top metal layer, and another one of the bonding vias is directly in contact with the bottom metal layer.

### Claim 4 (depends on 3)

The package of claim 3, wherein the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and a material of the dielectric layers of the first interconnection structure is different from a material of the insulating layer of the first capacitor.

### Claim 5 (depends on 2)

The package of claim 2, wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, the insulating layer and the top metal layer comprise an opening exposing the bottom metal layer, and at least one of the bonding vias extends into the opening to contact the bottom metal layer.

### Claim 6 (depends on 2)

The package of claim 2, wherein the first die further comprises a third capacitor embedded in the passivation layer, and the third capacitor is electrically connected to the first capacitor and the second capacitor.

### Claim 7 (depends on 1)

The package of claim 1, further comprising:
a redistribution structure disposed on the second die and the encapsulant; and
through insulating vias (TIV) electrically connecting the first die and the redistribution structure.

### Claim 8 (depends on 7)

The package of claim 7, wherein the second die further comprises a semiconductor substrate, through semiconductor vias (TSV) penetrating through the semiconductor substrate, and a second interconnection structure disposed on the semiconductor substrate, and the TSVs electrically connect the second interconnection structure and the redistribution structure.

### Claim 9

A package, comprising:
a first die, comprising:
a first interconnection structure; and
a second die stacked on the first die, comprising:
a second interconnection structure;
a passive device, comprising a first MIM structure and a second MIM structure electrically connected to the first MIM structure, wherein the first MIM structure is embedded in the first interconnection structure, the second MIM structure is embedded in the second interconnection structure, and the first MIM structure comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order; and
an encapsulant laterally encapsulating the second die.

### Claim 10 (depends on 9)

The package of claim 9, wherein the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and a material of the dielectric layers of the first interconnection structure is different from a material of the insulating layer.

### Claim 11 (depends on 9)

The package of claim 9, wherein the first die further comprises first bonding vias partially embedded in the first interconnection structure, the insulating layer and the top metal layer comprise an opening exposing the bottom metal layer, and at least one of the first bonding vias extends into the opening to contact the bottom metal layer.

### Claim 12 (depends on 9)

The package of claim 9, further comprising:
a redistribution structure disposed on the second die and the encapsulant; and
through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs electrically connect the first die and the redistribution structure.

### Claim 13 (depends on 12)

The package of claim 12, wherein the first die further comprises first bonding vias partially embedded in the first interconnection structure and first bonding pads over the first interconnection structure, the second die further comprises second bonding vias partially embedded in the second interconnection structure and second bonding pads over the second interconnection structure, the first bonding vias are connected to the first bonding pads, the second bonding vias are connected to the second bonding pads, and sidewalls of each first bonding pad are aligned with sidewalls of the corresponding second bonding pad.

### Claim 14 (depends on 13)

The package of claim 13, wherein the first die further comprises third bonding pads levelled with the first bonding pads, and the TIVs are in direct contact with the third bonding pads.

### Claim 15

A manufacturing method of a package, comprising:
providing a wafer substrate having a first interconnection structure, wherein a first capacitor is formed in the first interconnection structure;
providing a die having a second interconnection structure, wherein a second capacitor is formed in the second interconnection structure;
bonding the die to the wafer substrate such that the first capacitor is electrically connected to the second capacitor; and
laterally encapsulating the die by an encapsulant.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and the bottom metal layer of the first capacitor and one of the conductive patterns are simultaneously formed.

### Claim 17 (depends on 16)

The method of claim 16, wherein the wafer substrate further comprises bonding vias partially embedded in the first interconnection structure, and providing the wafer substrate further comprises:
forming an opening in the top metal layer and the insulating layer to expose the bottom metal layer, wherein at least one of the bonding vias extends into the opening to contact the bottom metal layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein providing the wafer substrate further comprises:
forming a third capacitor over the first interconnection structure; and
forming a first passivation layer on the first interconnection structure to cover the third capacitor.

### Claim 19 (depends on 18)

The method of claim 18, wherein providing the dies further comprises:
forming a fourth capacitor over the second interconnection structure; and
forming a second passivation layer on the second interconnection structure to cover the fourth capacitor.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
forming a redistribution structure over the die and the encapsulant; and
forming through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs electrically connect the wafer substrate and the redistribution structure.