# US 12,218,106 B2 · Backside contact to improve thermal dissipation away from semiconductor devices

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- Number: US 12,218,106 B2
- Document ID: US12218106B2
- Status: Granted
- Kind: B2
- Application number: 18/358,186
- Filed: 2023-07-25
- Published: 2023-11-16
- Granted: 2025-02-04
- Earliest claimed: 2020-06-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Min-Feng Kao; Dun-Nian Yaung; Hsing-Chih Lin; Jen-Cheng Liu; Yi-Shin Chu; Ping-Tzu Chen; Che-Wei Chen
- Web page: https://patentgrep.com/patent/US12218106B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/965: {Providing thermal transfer}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

## Claims

### Claim 1

A three-dimensional (3D) integrated circuit (IC) stack comprising:
a first semiconductor substrate including a first integrated circuit;
a second semiconductor substrate including a second integrated circuit, the second semiconductor substrate arranged over the first semiconductor substrate; and
a first backside contact extending from a backside of the second semiconductor substrate and being thermally coupled to an interconnect structure of the first integrated circuit or the second integrated circuit; and
a through substrate via (TSV) extending through the second semiconductor substrate from the backside of the second semiconductor substrate to a frontside of the second semiconductor substrate, wherein the TSV is laterally spaced apart from the first backside contact.

### Claim 2 (depends on 1)

The 3D IC stack of claim 1, wherein the TSV is not electrically coupled to the first backside contact.

### Claim 3 (depends on 1)

The 3D IC stack of claim 1, wherein a topmost surface of the first backside contact is arranged below a topmost surface of the TSV, wherein a bottommost surface of the TSV is arranged below the bottommost surface of the first backside contact.

### Claim 4 (depends on 1)

The 3D IC stack of claim 1, wherein the second semiconductor substrate comprises a second semiconductor device, and wherein the first backside contact directly overlies the second semiconductor device.

### Claim 5 (depends on 1)

The 3D IC stack of claim 1, wherein the first backside contact comprises tungsten, and wherein the interconnect structure comprises copper.

### Claim 6 (depends on 1)

The 3D IC stack of claim 1, wherein the first backside contact has an outermost sidewall that is curved when viewed in cross-section.

### Claim 7 (depends on 1)

The 3D IC stack of claim 1, wherein the first backside contact is spaced from the second semiconductor substrate by a glue layer.

### Claim 8

An integrated circuit (IC) die comprising:
a semiconductor substrate;
a transistor arranged on a frontside of the semiconductor substrate;
a first bond feature arranged over the frontside of the semiconductor substrate;
a second bond feature arranged on a backside of the semiconductor substrate;
a backside contact arranged within the second bond feature, wherein a bottommost surface of the backside contact is thermally coupled to the backside of the semiconductor substrate, wherein a topmost surface of the backside contact is arranged spaced apart from a bottommost surface of the semiconductor substrate; and
a through substrate via (TSV) extending through the semiconductor substrate and coupled to the second bond feature, wherein a topmost surface of the TSV is above the topmost surface of the backside contact.

### Claim 9 (depends on 8)

The IC die of claim 8, wherein the TSV is arranged laterally beside the transistor, and wherein the backside contact is arranged directly above the transistor.

### Claim 10 (depends on 8)

The IC die of claim 8, wherein the backside contact and the TSV are coupled to a bond pad arranged within a third bond feature bonded to the second bond feature.

### Claim 11 (depends on 10)

The IC die of claim 10, wherein the bond pad comprises metal.

### Claim 12 (depends on 8)

The IC die of claim 8, wherein the backside contact has a higher thermal conductivity than the TSV.

### Claim 13 (depends on 8)

The IC die of claim 8, wherein the TSV comprises copper and the backside contact comprises tungsten.

### Claim 14 (depends on 8)

The IC die of claim 8, wherein the backside contact is spaced from the semiconductor substrate by a glue layer.

### Claim 15 (depends on 8)

The IC die of claim 8 further comprising:
an additional backside contact arranged within the second bond feature and coupled to the second bond feature, wherein the additional backside contact is spaced apart from the backside contact by the semiconductor substrate, and wherein the additional backside contact and the backside contact are arranged directly above the transistor.

### Claim 16

A method of forming an integrated circuit, the method comprising:
forming a semiconductor device on a frontside of a semiconductor substrate;
depositing a first dielectric layer over a backside of the semiconductor substrate;
patterning the first dielectric layer to form a first opening in the first dielectric layer, wherein the first opening exposes a surface of the backside of the semiconductor substrate;
form a backside contact in the first opening;
depositing a second dielectric layer over the first dielectric layer and the backside contact;
patterning the second dielectric layer and the first dielectric layer to form a second opening that extends completely through the first dielectric layer, the second dielectric layer, and the semiconductor substrate;
forming a through substrate via (TSV) in the second opening; and
forming more dielectric layers, bonding vias, and bonding wire layers over the second dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, wherein the backside contact is coupled to the bonding vias and the bonding wire layers.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming of the backside contact is performed before the forming of the TSV.

### Claim 18 (depends on 16)

The method of claim 16, wherein the backside contact has a higher thermal conductivity than the TSV.

### Claim 19 (depends on 16)

The method of claim 16, wherein the TSV has a topmost surface that is above a topmost surface of the backside contact when the backside of the semiconductor substrate is above the frontside of the semiconductor substrate.

### Claim 20 (depends on 19)

The method of claim 19, wherein the topmost surface of the TSV is above the topmost surface of the backside contact by a first distance, and wherein the first distance is equal to a thickness of the second dielectric layer.