# US 12,218,103 B2 · Radiation hardened semiconductor devices and packaging

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,103 B2
- Document ID: US12218103B2
- Status: Granted
- Kind: B2
- Application number: 17/825,695
- Filed: 2022-05-26
- Published: 2023-11-30
- Granted: 2025-02-04
- Earliest claimed: 2022-05-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Chong Leong Gan
- Web page: https://patentgrep.com/patent/US12218103B2

## CPC

- H10W 90/00: Package configurations
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/271: {the arrangements being between stacked chips}
- H10W 72/01: {Manufacture or treatment}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Radiation hard semiconductor devices and packaging are disclosed. A semiconductor device assembly includes a substrate, a semiconductor die stack electrically coupled to the substrate, and an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC). The semiconductor device assembly further includes an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.

## Claims

### Claim 1

A semiconductor device assembly comprising:
a substrate;
a semiconductor die stack electrically coupled to the substrate;
an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC); and
an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1, wherein the ionizing radiation shield has approximately equal plan dimensions to those of the top die.

### Claim 3 (depends on 1)

The semiconductor device assembly of claim 1, wherein the ionizing radiation shield further comprises graphene.

### Claim 4 (depends on 1)

The semiconductor device assembly of claim 1, wherein at least one die of the semiconductor die stack comprises a silicon carbide layer coupled to an epitaxial layer of graphene or carbon nanotubes.

### Claim 5 (depends on 1)

The semiconductor device assembly of claim 1, further comprising:
a plurality of vias disposed within the substrate, the plurality of vias including carbon nanotubes and electrically coupled to a grounding pin of the semiconductor die stack.

### Claim 6 (depends on 1)

The semiconductor device assembly of claim 1, further comprising:
a graphene layer disposed on a top surface of the substrate that is electrically coupled to the semiconductor die stack.

### Claim 7 (depends on 1)

The semiconductor device assembly of claim 1, wherein the semiconductor die stack comprises a stack of memory dies.

### Claim 8 (depends on 7)

The semiconductor device assembly of claim 7, further comprising:
an interposer disposed between the substrate and the semiconductor die stack, the interposer including a first surface facing toward the semiconductor die stack and a second surface facing toward the substrate; and
a processor die coupled to the first surface of the interposer, wherein the processor die includes another ionizing radiation shield.

### Claim 9 (depends on 1)

The semiconductor device assembly of claim 1, wherein the semiconductor die stack is flip-chip bonded to the substrate.

### Claim 10 (depends on 1)

The semiconductor device assembly of claim 1, wherein the semiconductor die stack includes a through silicon via (TSV) comprised of carbon nanotubes.

### Claim 11

A method of producing a semiconductor device assembly comprising:
attaching a semiconductor die stack to a substrate;
disposing an ionizing radiation shield comprising silicon carbide (SiC) above a top die of the semiconductor die stack; and
at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.

### Claim 12 (depends on 11)

The method of claim 11, wherein the ionizing radiation shield further comprises graphene.

### Claim 13 (depends on 11)

The method of claim 11, wherein the ionizing radiation shield has approximately equal plan dimensions to those of the top die.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
forming a plurality of vias in the substrate, the plurality of vias including carbon nanotubes.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
forming a graphene layer a top surface of the substrate; and
electrically coupling a ground pin of the semiconductor die stack to the graphene layer.

### Claim 16 (depends on 11)

The method of claim 11, wherein the semiconductor die stack comprises a stack of memory dies.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
disposing an interposer between the substrate and the semiconductor die stack, the interposer including a first surface facing toward the die stack and a second surface facing toward the substrate;
forming a second ionizing radiation shield on a processor die; and
attaching the processor die to the first surface of the interposer.

### Claim 18 (depends on 11)

The method of claim 11, wherein attaching the semiconductor die stack to the substrate includes flip-chip bonding a die of the semiconductor stack to the substrate.

### Claim 19

A semiconductor device assembly comprising:
a semiconductor die stack, wherein each semiconductor die of the semiconductor die stack includes a passivation layer and a first graphene layer formed on the passivation layer;
an ionizing radiation shield positioned above the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC);
an encapsulant at least partially encapsulating the ionizing radiation shield and the semiconductor die stack; and
a substrate electrically coupled to the semiconductor die stack, wherein the substrate includes a graphene layer positioned on a surface facing the semiconductor die stack, the graphene layer configured to provide electrical grounding for the semiconductor die stack.

### Claim 20 (depends on 19)

The semiconductor device assembly of claim 19, further comprising:
an interposer disposed between the substrate and the semiconductor die stack, the interposer including a first surface facing toward the semiconductor die stack and a second surface facing toward the substrate; and
a processor die coupled to the first surface of the interposer, wherein the processor die includes another ionizing radiation shield.