# US 12,218,102 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,102 B2 - Document ID: US12218102B2 - Status: Granted - Kind: B2 - Application number: 17/728,727 - Filed: 2022-04-25 - Published: 2023-03-09 - Granted: 2025-02-04 - Earliest claimed: 2021-09-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Youngkun Jee; Unbyoung Kang; Sanghoon Lee; Chungsun Lee - Web page: https://patentgrep.com/patent/US12218102B2 ## CPC - H10W 90/00: Package configurations - H10W 40/253: {Semiconductors} - H10W 40/778: {in encapsulations} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/30: Die-attach connectors - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 80/334: {Thermocompression bonding} - H10W 80/701: {characterised by the pads after the direct bonding} - H10W 90/20: Configurations of stacked chips - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/732: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof. ## Claims ### Claim 1 A semiconductor package comprising: a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, and the first semiconductor chip including a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate; a plurality of second semiconductor chips including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, the active surface of the second semiconductor substrate facing the inactive surface of the first semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip; a plurality of bonding pads arranged between the first semiconductor chip and the plurality of second semiconductor chips; a chip bonding insulating layer configured to surround the plurality of bonding pads and arranged between the first semiconductor chip and the plurality of second semiconductor chips; and at least one supporting dummy substrate stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof, wherein at least some of the plurality of second semiconductor chips comprise a plurality of second through electrodes penetrating at least a portion of the second semiconductor substrate, wherein the plurality of bonding pads electrically connect the plurality of first through electrodes to the plurality of second through electrodes, wherein a total vertical height of the at least one supporting dummy substrate is greater than respective vertical heights of the first semiconductor chip and the plurality of second semiconductor chips. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the at least one supporting dummy substrate includes a plurality of supporting dummy substrates stacked on the plurality of second semiconductor chips, and respective vertical heights of at least some of the plurality of supporting dummy substrates are equal to or less than respective vertical heights of the first semiconductor chip and the plurality of second semiconductor chips. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein a vertical height of an uppermost supporting dummy substrate among the plurality of supporting dummy substrates is less than a vertical height of remaining supporting dummy substrates among the plurality of supporting dummy substrates. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein a vertical height of an uppermost supporting dummy substrate among the plurality of supporting dummy substrates is greater than respective vertical heights of each of remaining supporting dummy substrates among the plurality of supporting dummy substrates, the first semiconductor chip, and the plurality of second semiconductor chips. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein only one supporting dummy substrate having a vertical height greater than respective vertical heights of each of the first semiconductor chip and the plurality of second semiconductor chips is stacked on the plurality of second semiconductor chips. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein horizontal widths of the plurality of second semiconductor chips are less than horizontal widths of the first semiconductor chip, wherein a horizontal width of the at least one supporting dummy substrate is less than a horizontal width of the plurality of second semiconductor chips. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein, in the support bonding insulating layer covering an upper surface of an uppermost second semiconductor chip among the plurality of second semiconductor chips, a thickness of a portion vertically overlapping with the at least one supporting dummy substrate is greater than that of a portion not vertically overlapping with the at least one supporting dummy substrate. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein, in a chip bonding insulating layer covering an upper surface of the first semiconductor chip, a thickness of a portion overlapping with the plurality of second semiconductor chips in a vertical direction has a larger value than a portion that does not vertically overlap with the plurality of second semiconductor chips. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the at least one supporting dummy substrate is a part of a bare wafer, wherein an uppermost second semiconductor chip among the plurality of second semiconductor chips does not have the second through electrodes, wherein upper and lower surfaces of the support bonding insulating layer are in contact only with a semiconductor material. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of bonding pads, the chip bonding insulating layer, and the support bonding insulating layer is diffusion bonded to form an integral body. ### Claim 11 A semiconductor package comprising: a high bandwidth memory (HBM) controller die including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, and the HBM controller die including a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate; a plurality of dynamic random access memory (DRAM) dies including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, the active surface of the second semiconductor substrate facing the inactive surface of the first semiconductor substrate, the plurality of DRAM dies being stacked on the first semiconductor substrate; a plurality of bonding pads arranged between the HBM controller die and the plurality of DRAM dies; a chip bonding insulating layer configured to surround the plurality of bonding pads and arranged between the HBM controller die and the plurality of DRAM dies; and a plurality of supporting dummy substrates sequentially stacked on the plurality of DRAM dies and having a support bonding insulating layer attached to each lower surface thereof, wherein remaining DRAM dies except for an uppermost DRAM die among the plurality of DRAM dies comprises a plurality of second through electrodes penetrating at least a portion of the second semiconductor substrate and electrically connected to the plurality of first through electrodes through the plurality of bonding pads, wherein a vertical height of each of the plurality of supporting dummy substrates are equal to or less than a respective vertical heights of each of the first semiconductor substrate and the plurality of DRAM dies, wherein a total vertical height of the plurality of supporting dummy substrates is greater than respective vertical heights of the first semiconductor substrate and the plurality of DRAM dies. ### Claim 12 (depends on 11) The semiconductor package of claim 11, further comprising: on the HBM controller die, a package molding layer that covers an upper surface of the HBM controller die, side surfaces of the plurality of DRAM dies, and side surfaces of the plurality of supporting dummy substrates, but exposes an upper surface of an uppermost supporting dummy substrate among the plurality of supporting dummy substrates without covering the upper surface of the uppermost supporting dummy substrate. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein a vertical height of each of the plurality of supporting dummy substrates is equal to each other. ### Claim 14 (depends on 11) The semiconductor package of claim 11, wherein a vertical height of an uppermost supporting dummy substrate among the plurality of supporting dummy substrates is less than a vertical height of the remaining supporting dummy substrates among the plurality of supporting dummy substrates, wherein a vertical height of each of the remaining supporting dummy substrates except for the uppermost supporting dummy substrate among the plurality of supporting dummy substrates are equal. ### Claim 15 (depends on 11) The semiconductor package of claim 11, wherein the support bonding insulating layer is spaced apart from the plurality of second through electrodes without contacting. ### Claim 16 (depends on 11) The semiconductor package of claim 11, wherein each of the plurality of supporting dummy substrates has a same horizontal width as each other, which is less than a horizontal width of the plurality of DRAM dies. ### Claim 17 (depends on 11) The semiconductor package of claim 11, wherein the support bonding insulating layer filling between an upper surface of the uppermost DRAM die among the plurality of DRAM dies and a lowermost supporting dummy substrate among the plurality of supporting dummy substrates has a center portion protruding above an edge portion and has a flat lower surface. ### Claim 18 A semiconductor package comprising: a high bandwidth memory (HBM) controller die including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, and the HBM controller die including a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate, the HBM controller die having a first horizontal width and a first vertical height; a plurality of dynamic random access memory (DRAM) dies including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, the active surface of the second semiconductor substrate facing the inactive surface of the first semiconductor substrate and is stacked on a first semiconductor chip, the plurality of DRAM dies each having a second horizontal width less than the first horizontal width and a second vertical height; a plurality of bonding pads arranged between the HBM controller die and the plurality of DRAM dies; a chip bonding insulating layer configured to surround the plurality of bonding pads and arranged between the HBM controller die and the plurality of DRAM dies; a plurality of supporting dummy substrates having a support bonding insulating layer attached to each lower surface thereof and sequentially stacked on the plurality of DRAM dies, and each having a third horizontal width less than the second horizontal width and a third vertical height equal to or less than the first vertical height and the second vertical height; and a package molding layer that covers an upper surface of the HBM controller die, side surfaces of the plurality of DRAM dies, and side surfaces of the plurality of supporting dummy substrates, but exposes an upper surface of an uppermost supporting dummy substrate among the plurality of supporting dummy substrates without covering the upper surface of the uppermost supporting dummy substrate, wherein vertical heights of the plurality of supporting dummy substrates are greater than the first vertical height and the second vertical height. ### Claim 19 (depends on 18) The semiconductor package of claim 18, wherein the third vertical height is about 50 μm to about 90 μm, wherein a total vertical height of the plurality of supporting dummy substrates is about 100 μm to about 500 μm. ### Claim 20 (depends on 18) The semiconductor package of claim 18, wherein the plurality of bonding pads comprise a material containing Cu, wherein each of the chip bonding insulating layer and the support bonding insulating layer comprises silicon oxide.