# US 12,218,099 B2 · Interposer and semiconductor package including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,099 B2 - Document ID: US12218099B2 - Status: Granted - Kind: B2 - Application number: 17/392,511 - Filed: 2021-08-03 - Published: 2021-11-25 - Granted: 2025-02-04 - Earliest claimed: 2018-12-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jungsoo Byun; Taesung Jeong; Younggwan Ko; Jaeean Lee - Web page: https://patentgrep.com/patent/US12218099B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10W 90/00: Package configurations - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers} - H10W 70/635: {Through-vias} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/63: Vias, e.g. via plugs - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips. ## Claims ### Claim 1 A semiconductor package comprising: an interposer including a first connection structure having a first redistribution conductor, a plurality of second connection structures each having a second redistribution conductor and disposed around the first connection structure, a plurality of third connection structures each having a third redistribution conductor and disposed between the first connection structure and the plurality of second connection structures, and a passivation layer filling spaces between the first connection structure, the plurality of second connection structures, and the plurality of third connection structures; a first semiconductor chip disposed on the interposer to overlap the first connection structure and at least a portion of the plurality of third connection structures, in a stacking direction of the first semiconductor chip on the interposer; a second semiconductor chip disposed on the interposer to overlap at least a portion of the plurality of second connection structures and at least a portion of the plurality of third connection structures, in a stacking direction of the second semiconductor chip on the interposer; and a plurality of electrical connection structures disposed below the interposer, and electrically connected to the first semiconductor chip and the second semiconductor chip, wherein the first redistribution conductor electrically connects the first semiconductor chip to at least a portion of the plurality of electrical connection structures, the second redistribution conductor electrically connects the second semiconductor chip to at least a portion of the plurality of electrical connection structures, and the third redistribution conductor electrically connects the first semiconductor chip and the second semiconductor chip to each other, wherein each of the first connection structure, the plurality of second connection structures, and the plurality of third connection structures further includes a plurality of insulation layers, wherein each of the first redistribution conductor, the second redistribution conductor, and the third redistribution conductor includes a plurality of redistribution layers disposed in or on the plurality of insulation layers, and a plurality of connection vias penetrating each of the plurality of insulation layers and electrically connecting the plurality of redistribution layers to each other, wherein the passivation layer and each of the plurality of insulation layers includes a photosensitive insulation layer, wherein each of the plurality of insulation layers is a positive-type photosensitive insulation layer, and wherein the passivation layer is a negative-type photosensitive insulation layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first connection structure has a first side and a second side opposing each other, the plurality of second connection structures includes a first group of second connection structure disposed adjacent to the first side, and a second group of second connection structure disposed adjacent to the second side. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the first group of second connection structure and the second group of second connection structure include an equal number of second connection structure. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein the plurality of third connection structures includes a first group of third connection structure disposed between the first group of second connection structure and the first side, and a second group of third connection structure disposed between the second group of second connection structure and the second side. ### Claim 5 (depends on 4) The semiconductor package of claim 4, wherein the first group of third connection structure and the second group of third connection structure include an equal number of third connection structure. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the plurality of redistribution layers of each of the first to third redistribution conductors have an equal number of layers. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the first to third connection structures have a thickness substantially the same as each other. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the first semiconductor chip includes a graphics processing unit (GPU), and the second semiconductor chip includes a high bandwidth memory (HBM). ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the second semiconductor chip is provided with a plurality of second semiconductor chips disposed adjacent to the first semiconductor chip. ### Claim 10 A semiconductor package comprising: an interposer including a first connection structure having a first redistribution conductor, a second connection structure having a second redistribution conductor, and a third connection structure disposed between the first connection structure and the second connection structure, the third connection structure having a third redistribution conductor, the first to third connection structures being spaced apart from each other; a first semiconductor chip disposed on the first connection structure and the third connection structure; a second semiconductor chip disposed on the second connection structure and the third connection structure; an encapsulant disposed on the interposer and covering each of the first semiconductor chip and the second semiconductor chip; and a plurality of electrical connection structures disposed below the interposer, and electrically connected to the first semiconductor chip and the second semiconductor chip, wherein the first redistribution conductor electrically connects the first semiconductor chip to at least a portion of the plurality of electrical connection structures, the second redistribution conductor electrically connects the second semiconductor chip to at least a portion of the plurality of electrical connection structures, the third redistribution conductor electrically connects the first semiconductor chip and the second semiconductor chip to each other the interposer further includes a passivation layer filling spaces between the first connection structure, the second connection structure, and the third connection structure, and a side surface of the passivation layer is coplanar with a side surface of the encapsulant, wherein each of the first connection structure, the second connection structure, and the third connection structure further includes a plurality of insulation layers, wherein each of the first redistribution conductor, the second redistribution conductor, and the third redistribution conductor includes a plurality of redistribution layers disposed in or on the plurality of insulation layers, and a plurality of connection vias penetrating each of the plurality of insulation layers and electrically connecting the plurality of redistribution layers to each other, wherein the passivation layer and each of the plurality of insulation layers includes a photosensitive insulation layer, wherein each of the plurality of insulation layers is a positive-type photosensitive insulation layer, and wherein the passivation layer is a negative-type photosensitive insulation layer. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein each of the first connection structure, the second connection structure and the third connection structure is provided in plural, and a number of each of the second connection structures and the third connection structures is larger than a number of the first connection structures. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein the first to third redistribution conductors are electrically insulated from each other. ### Claim 13 (depends on 10) The semiconductor package of claim 10, further comprising a plurality of connection members electrically connecting the first semiconductor chip and the second semiconductor chip to the first redistribution conductor, the second redistribution conductor, and the third redistribution conductor. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the plurality of connection members comprise a low melting point metal selected from a group consisting of tin (Sn), and alloys containing tin (Sn). ### Claim 15 (depends on 10) The semiconductor package of claim 10, wherein each of the first semiconductor chip and the second semiconductor chip is provided in plural and a number of the second semiconductor chips is larger than a number of the first semiconductor chips. ### Claim 16 A semiconductor package comprising: a printed circuit board; an interposer disposed on the printed circuit board, and including a first connection structure having a first redistribution conductor, a second connection structure having a second redistribution conductor, and a third connection structure disposed between the first connection structure and the second connection structure, the third connection structure having a third redistribution conductor; a first semiconductor chip disposed on the interposer to overlap the first connection structure and the third connection structure, in a stacking direction of the first semiconductor chip on the interposer; a second semiconductor chip disposed on the interposer to overlap the second connection structure and the third connection structure, in a stacking direction of the second semiconductor chip on the interposer; and an encapsulant disposed on the interposer and covering each of the first semiconductor chip and the second semiconductor chip, wherein the first redistribution conductor redistributes the first semiconductor chip, the second redistribution conductor redistributes the second semiconductor chip, the third redistribution conductor electrically connects the first semiconductor chip and the second semiconductor chip to each other, the interposer further includes a passivation layer filling spaces between the first connection structure, the second connection structure, and the third connection structure, and a side surface of the passivation layer is coplanar with a side surface of the encapsulant, wherein each of the first connection structure, the second connection structure, and the third connection structure further includes a plurality of insulation layers, wherein each of the first redistribution conductor, the second redistribution conductor, and the third redistribution conductor includes a plurality of redistribution layers disposed in or on the plurality of insulation layers, and a plurality of connection vias penetrating each of the plurality of insulation layers and electrically connecting the plurality of redistribution layers to each other, wherein the passivation layer and each of the plurality of insulation layers includes a photosensitive insulation layer, wherein each of the plurality of insulation layers is a positive-type photosensitive insulation layer, and wherein the passivation layer is a negative-type photosensitive insulation layer.