# US 12,218,098 B2 · Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

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- Number: US 12,218,098 B2
- Document ID: US12218098B2
- Status: Granted
- Kind: B2
- Application number: 17/722,929
- Filed: 2022-04-18
- Published: 2022-07-28
- Granted: 2025-02-04
- Earliest claimed: 2014-02-04
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Petteri Palm; Thorsten Scharf; Ralf Wombacher
- Web page: https://patentgrep.com/patent/US12218098B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 76/153: having interconnections in passages through the insulating or insulated base
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/874: {On different surfaces}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

## Claims

### Claim 1

An electronic module, comprising:
an electrically conductive first substrate;
a first dielectric layer on the first substrate;
an electronic chip, which is mounted with a first main surface directly or on a section of the first dielectric layer;
an electrically conductive second substrate over a second main surface of the at least one electronic chip;
a second dielectric layer on the second substrate, wherein the electronic chip is mounted with its second main surface directly on a section of the second dielectric layer;
an electrical contacting for electrically contacting a first pad of the at least one electronic chip on the first main surface of the at least one electronic chip through the first dielectric layer;
a further electrical contacting for electrically contacting a second pad of the at least one electronic chip on the second main surface of the at least one electronic chip through a plurality of clearance boles penetrating the second dielectric layer;
wherein the first dielectric layer on the first substrate extends across an area, which exceeds the first main surface, and
wherein the first dielectric layer is formed by a first partial layer on the first substrate and a separate second partial layer on the first partial layer where the first partial layer is between the first substrate and the second partial layer, the first partial layer and the second partial layer comprising different material compositions.

### Claim 2 (depends on 1)

The electronic module according to claim 1, comprising a dielectric structure, in particular a laminate structure, to fill in completely at least one hollow space, which is delimited between the first dielectric layer, the second dielectric layer and the at least one electronic chip.

### Claim 3 (depends on 1)

The electronic module according to claim 1, wherein at least one of the first substrate and of the second substrate is a structured foil.

### Claim 4 (depends on 1)

The electronic module according to claim 1, wherein the first dielectric layer is formed of a full-surface layer with at least one through-hole, which is filled with an electrically conductive material, as electrical contact for electrically contacting the first main surface of the at least one electronic chip.

### Claim 5 (depends on 1)

The electronic module according to claim 1, comprising a plurality of electronic chips, wherein each electronic chip is mounted with its first main surface on the first dielectric layer in such way, that a part of the first dielectric layer remains uncovered of the plurality of electronic chips.

### Claim 6 (depends on 1)

The electronic module according to claim 1, wherein the at least one electronic chip is configured as a power semiconductor chip.

### Claim 7 (depends on 1)

The electronic module according to claim 1, comprising two electronic chips, wherein one of them has its active side on its first main surface and the other one has its active side on its second main surface.

### Claim 8 (depends on 1)

The electronic module according to claim 1, comprising a plurality of electronic chips, which are electrically coupled with each other on at least one of the first main surface and the second main surface by the electrical contacting.

### Claim 9 (depends on 1)

The electronic module according to claim 1, comprising at least one through hole filled with electrically conductive material, which extends perpendicular to the first substrate and the second substrate to form an electrical coupling of the first substrate with the second substrate.

### Claim 10 (depends on 1)

The electronic module according to claim 1, where the first dielectric layer comprises an adhesive material.

### Claim 11 (depends on 10)

The electronic module according to claim 10, where the adhesive material is a hardened adhesive material.

### Claim 12 (depends on 11)

The electronic module according to claim 11, where the hardened adhesive material is a hardened polymer adhesion layer.

### Claim 13 (depends on 1)

The electronic module according to claim 1, where the first partial layer is made of a hardened polymer adhesive material.

### Claim 14 (depends on 1)

The electronic module according to claim 1, wherein the clearance holes comprise micro vias.

### Claim 15

An electronic module, comprising:
a first substrate;
a first dielectric layer on the first substrate;
an electronic chip, which is mounted with a first main surface directly or on a section of the first dielectric layer;
a second substrate over a second main surface of the at least one electronic chip;
an electrical contacting for electrically contacting a first pad of the at least one electronic chip on the first main surface of the at least one electronic chip through the first dielectric layer,
wherein the first dielectric layer on the first substrate extends across an area, which exceeds the first main surface;
a second dielectric layer on the second substrate, wherein the electronic chip is mounted with its second main surface directly on a section of the second dielectric layer;
a further electrical contacting for electrically contacting a second pad of the at least one electronic chip on the second main surface of the at least one electronic chip through a plurality of clearance holes penetrating the second dielectric layer;
a dielectric structure, in particular a laminate structure, to fill in completely at least one hollow space, which is delimited between the first dielectric layer, the second dielectric layer and the at least one electronic chip;
wherein at least one of the first substrate and of the second substrate is a structured foil, and
wherein the first dielectric layer is formed by a first partial layer on the first substrate and a separate second partial layer on the first partial layer where the first partial layer is between the first substrate and the second partial layer, the first partial layer and the second partial layer comprising different material compositions.

### Claim 16 (depends on 15)

The electronic module according to claim 15, wherein the first dielectric layer is formed of a full-surface layer with at least one through-hole, which is filled with an electrically conductive material, as electrical contact for electrically contacting the first main surface of the at least one electronic chip, and
a plurality of electronic chips, wherein each electronic chip is mounted with its first main surface on the first dielectric layer in such way, that a part of the first dielectric layer remains uncovered of the plurality of electronic chips.

### Claim 17 (depends on 16)

The electronic module according to claim 16, wherein the at least one electronic chip is configured as a power semiconductor chip having a half-bridge configuration.

### Claim 18

An electronic module comprising:
a dielectric structural layer;
a chip embedded in the dielectric structural layer, the chip including a first main surface and a second main surface;
a first dielectric layer positioned over the dielectric structural layer and extending partially over the first main surface;
an electrical contacting for electrically contacting a first pad of the chip on the first main surface of the chip through plurality of clearance holes penetrating the first dielectric layer;
an electrically conductive first substrate positioned on the first dielectric layer and the first main surface,
where the dielectric structural layer extends beyond and partially covers the second main surface, and an electric contact via extending through the structural layer for electrically contacting a second pad of the chip on the second main surface of the chip;
a second dielectric layer positioned over the dielectric structural layer, where the second dielectric layer partially extends into the via; and
an electrically conductive second substrate positioned over the second dielectric layer,
wherein the first dielectric layer is formed by a first partial layer over the dielectric structural layer and the first main surface and a separate second partial layer on the first partial layer where the first partial layer is between the first substrate and the second partial layer, the first partial layer and the second partial layer comprising different material compositions.

### Claim 19 (depends on 18)

The electronic module of claim 18, comprising where the first dielectric layer comprises a hardened polymer adhesive layer that forms a dielectric material.

### Claim 20 (depends on 19)

The electronic module of claim 19, where the first substrate layer is structured at the first main surface.