# US 12,218,097 B2 · Bonding to alignment marks with dummy alignment marks

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- Number: US 12,218,097 B2
- Document ID: US12218097B2
- Status: Granted
- Kind: B2
- Application number: 18/364,310
- Filed: 2023-08-02
- Published: 2023-11-23
- Granted: 2025-02-04
- Earliest claimed: 2021-03-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Ying-Ju Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US12218097B2

## CPC

- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 46/301: {for alignment}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 72/985: {Alignment aids, e.g. alignment marks}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/163: {using active alignment, e.g. detecting marks and correcting position}
- H10W 80/168: {using guiding structures}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/732: {having shape changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.

## Claims

### Claim 1

A method comprising:
placing a first package component, wherein the first package component comprises:
a first alignment mark; and
a first dummy alignment mark, wherein both of the first alignment mark and the first dummy alignment mark are electrically floating;
aligning a second package component to the first package component, wherein the second package component comprises:
a second alignment mark; and
a second dummy alignment mark, wherein both of the second alignment mark and the second dummy alignment mark are electrically floating, wherein the aligning comprises searching for a first pattern of the first alignment mark for positioning the first package component, and the aligning is performed ignoring a second pattern of the first dummy alignment mark; and
bonding the second package component to the first package component to form a package, wherein after the bonding, the first alignment mark is bonded to the second dummy alignment mark.

### Claim 2 (depends on 1)

The method of claim 1, wherein the aligning further comprises searching for a third pattern of the second alignment mark for positioning the second package component, and the aligning is performed ignoring a fourth pattern of the second dummy alignment mark.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first alignment mark comprises a first plurality of discrete features, the second dummy alignment mark comprises a second plurality of discrete features, and wherein the first plurality of discrete features are bonded to the second plurality of discrete features with a one-to-one correspondence.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first plurality of discrete features have same shapes and same sizes as corresponding ones of the second plurality of discrete features.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first alignment mark comprises a first plurality of discrete features, the second dummy alignment mark comprises a second plurality of discrete features, and wherein each of the first plurality of discrete features is smaller than a corresponding one of the second plurality of discrete features.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first alignment mark comprises a first plurality of discrete features disposed in a first top-view area of the first package component, and the first dummy alignment mark comprises a second plurality of discrete features disposed in a second top-view area of the first package component, and wherein the first top-view area and the second top-view area have a common area.

### Claim 7 (depends on 6)

The method of claim 6, wherein an entirety of the first top-view area is in the second top-view area.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first alignment mark and the first dummy alignment mark are formed in a same dielectric layer, and are formed by a same formation process.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first alignment mark comprises a first plurality of discrete features, the first dummy alignment mark comprises a second plurality of discrete features, and wherein the first plurality of discrete features and the second plurality of discrete features are interlaced.

### Claim 10 (depends on 1)

The method of claim 1, wherein a first surface dielectric layer in the first package component is bonded to a second surface dielectric layer in the second package component through fusion bonding, and the first alignment mark is bonded to the second dummy alignment mark through metal-to-metal direct bonding.

### Claim 11 (depends on 1)

The method of claim 1, wherein the second alignment mark is an embedded alignment mark, and after the bonding, the second alignment mark is physically spaced apart from the first package component.

### Claim 12 (depends on 1)

The method of claim 1, wherein the bonding the second package component to the first package component comprises bonding a second wafer to a first wafer.

### Claim 13

A method comprising:
providing a first wafer comprising:
a first alignment mark comprising a plurality of discrete metallic features having a first outer contour; and
a first dummy alignment mark having a second outer contour, wherein the first outer contour and the second outer contour have an overlapped region;
aligning the first wafer to a second wafer using the first alignment mark in the first wafer and a second alignment mark in the second wafer, wherein the second alignment mark is in a same chip area as a second dummy alignment mark in the second wafer; and
bonding the first wafer to the second wafer through hybrid bonding, wherein after the bonding, the first alignment mark in the first wafer is directly bonded to the second dummy alignment mark in the second wafer.

### Claim 14 (depends on 13)

The method of claim 13, wherein both of the first alignment mark and the second alignment mark are electrically floating.

### Claim 15 (depends on 13)

The method of claim 13, wherein each of the plurality of discrete metallic features is electrically floating.

### Claim 16 (depends on 13)

The method of claim 13, wherein the second alignment mark in the second wafer is embedded in the second wafer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second alignment mark comprises a ring, and in a top view of the second wafer and the first wafer, the ring encircles the first alignment mark and the first dummy alignment mark.

### Claim 18 (depends on 13)

The method of claim 13, wherein the aligning is performed by an aligner, and wherein in the aligning, the aligner searches for a first pattern of the first alignment mark, and the aligner ignores a second pattern of the first dummy alignment mark.

### Claim 19

A method comprising:
forming a first alignment mark and a first dummy alignment mark in a first wafer, wherein the first alignment mark is in a same first area of the first wafer as the first dummy alignment mark;
forming a second alignment mark and a second dummy alignment mark in a second wafer, wherein the second alignment mark is in a same second area of the second wafer as the second dummy alignment mark;
searching for a first pattern of the first alignment mark in the first wafer to find the first alignment mark;
searching for a second pattern of the second alignment mark in the second wafer to find the second alignment mark;
using the first alignment mark and the second alignment mark that have been found to align the first wafer and the second wafer; and
with the first wafer being aligned to the second wafer, bonding the second wafer to the first wafer.

### Claim 20 (depends on 19)

The method of claim 19, wherein each of the first alignment mark, the first dummy alignment mark, the second alignment mark, and the second dummy alignment mark is electrically floating.