# US 12,218,095 B2 · Chip package structure having molding layer

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- Number: US 12,218,095 B2
- Document ID: US12218095B2
- Status: Granted
- Kind: B2
- Application number: 18/361,196
- Filed: 2023-07-28
- Published: 2024-01-04
- Granted: 2025-02-04
- Earliest claimed: 2017-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shin-Puu Jeng; Shuo-Mao Chen; Feng-Cheng Hsu
- Web page: https://patentgrep.com/patent/US12218095B2

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/013: {of die-attach connectors}
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/019: {of bond pads}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 74/40: characterised by their materials
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and adjacent to the first chip. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a first molding layer over the first surface and surrounding the first chip. The chip package structure includes a second molding layer over the second surface and surrounding the second chip.

## Claims

### Claim 1

A chip package structure, comprising:
a first redistribution structure having a first surface and a second surface opposite to the first surface;
a first chip over the first surface;
a first conductive pillar over the first surface and adjacent to the first chip;
a second chip over the second surface;
a second conductive pillar over the second surface and adjacent to the second chip;
a first molding layer over the first surface and surrounding the first chip, wherein the first conductive pillar passes through the first molding layer, a first portion of the first molding layer covers a first bottom surface of the first chip, and the first bottom surface faces away from the first redistribution structure;
a second molding layer over the second surface and surrounding the second chip, wherein the second conductive pillar passes through the second molding layer, a second portion of the second molding layer covers a first top surface of the second chip, the first top surface faces away from the first redistribution structure, and
the first chip, the first redistribution structure, and the second chip are between the first portion of the first molding layer and the second portion of the second molding layer;
a second redistribution structure over the second chip;
a buffer layer between the second redistribution structure and the second chip;
a third chip over the second redistribution structure, wherein the second redistribution structure is between the third chip and the buffer layer; and
a conductive bump passing through the buffer layer and connected between the second conductive pillar and the second redistribution structure, wherein a width of the conductive bump continuously decreases from the second redistribution structure to the second conductive pillar.

### Claim 2 (depends on 1)

The chip package structure as claimed in claim 1, wherein a second bottom surface of the first molding layer is substantially level with a third bottom surface of the first conductive pillar.

### Claim 3 (depends on 2)

The chip package structure as claimed in claim 2, wherein a second top surface of the second molding layer is substantially level with a third top surface of the second conductive pillar.

### Claim 4 (depends on 3)

The chip package structure as claimed in claim 3, wherein the second bottom surface of the first molding layer is lower than the first bottom surface of the first chip.

### Claim 5 (depends on 4)

The chip package structure as claimed in claim 4, wherein the second top surface of the second molding layer is higher than the first top surface of the second chip.

### Claim 6 (depends on 5)

The chip package structure as claimed in claim 5, wherein a third portion of the first molding layer is between the first chip and the first redistribution structure, and a fourth portion of the second molding layer is between the second chip and the first redistribution structure.

### Claim 7 (depends on 1)

The chip package structure as claimed in claim 1, wherein the first conductive pillar and the second conductive pillar are arranged in a straight line, and the straight line is perpendicular to the first surface of the first redistribution structure.

### Claim 8 (depends on 1)

The chip package structure as claimed in claim 1, wherein the conductive bump has a trapezoid shape.

### Claim 9 (depends on 1)

The chip package structure as claimed in claim 1, wherein the second redistribution structure comprises a dielectric layer and a wiring layer, the wiring layer is over the dielectric layer, a portion of the wiring layer passes through the dielectric layer, and the conductive bump is in contact with the dielectric layer and the portion of the wiring layer.

### Claim 10

A chip package structure, comprising:
a redistribution structure having a first surface and a second surface opposite to the first surface;
a first chip over the first surface;
a first conductive pillar over the first surface;
a second chip over the second surface;
a second conductive pillar over the second surface;
a first molding layer over the first surface and surrounding the first chip, wherein the first conductive pillar passes through the first molding layer, a first portion of the first molding layer is between the first chip and the redistribution structure and in contact with a third surface of the first chip, and the third surface faces the redistribution structure;
an adhesive layer over the second chip, wherein the second chip is between the adhesive layer and the redistribution structure; and
a second molding layer over the second surface and surrounding the second chip, the adhesive layer and the second conductive pillar, wherein the adhesive layer is embedded in the second molding layer.

### Claim 11 (depends on 10)

The chip package structure as claimed in claim 10, wherein a first top surface of the second molding layer, a second top surface of the adhesive layer, and a third top surface of the second conductive pillar are substantially level with each other.

### Claim 12

A chip package structure, comprising:
a redistribution structure having a first surface and a second surface opposite to the first surface;
a first chip over the first surface;
an interposer over the first surface, wherein the interposer comprises a substrate and a conductive structure passing through the substrate;
a first molding layer over the first surface and surrounding the first chip and the interposer, wherein a portion of the first molding layer is between the redistribution structure and the interposer and separates the redistribution structure from the interposer;
a second chip over the second surface; and
a conductive bump passing through the portion of the first molding layer and connected between the interposer and the redistribution structure.

### Claim 13 (depends on 12)

The chip package structure as claimed in claim 12, wherein a first bottom surface of the first molding layer and a second bottom surface of the interposer are substantially level with each other.

### Claim 14 (depends on 13)

The chip package structure as claimed in claim 13, wherein the first bottom surface of the first molding layer, a third bottom surface of the substrate, and a fourth bottom surface of the conductive structure are substantially level with each other.

### Claim 15 (depends on 12)

The chip package structure as claimed in claim 12, further comprising:
a second molding layer over the second surface and surrounding the second chip.

### Claim 16 (depends on 15)

The chip package structure as claimed in claim 15, wherein a first sidewall of the first molding layer and a second sidewall of the second molding layer are substantially coplanar.

### Claim 17 (depends on 12)

The chip package structure as claimed in claim 12, wherein the interposer further comprises a wiring structure between the conductive structure and the redistribution structure, and the wiring structure is electrically connected to the redistribution structure and the conductive structure.

### Claim 18 (depends on 10)

The chip package structure as claimed in claim 10, wherein a first sidewall of the adhesive layer is connected to a second sidewall of the second chip, and the first sidewall and the second sidewall face the second conductive pillar.

### Claim 19 (depends on 10)

The chip package structure as claimed in claim 10, wherein a first top surface of the second molding layer and a second top surface of the adhesive layer are substantially level with each other.

### Claim 20 (depends on 10)

The chip package structure as claimed in claim 10, wherein the second conductive pillar passes through the second molding layer, a second portion of the second molding layer is between the second chip and the redistribution structure and in contact with a fourth surface of the second chip, and the fourth surface faces the redistribution structure.