# US 12,218,094 B2 · Electronic package structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,094 B2 - Document ID: US12218094B2 - Status: Granted - Kind: B2 - Application number: 18/610,185 - Filed: 2024-03-19 - Published: 2024-07-04 - Granted: 2025-02-04 - Earliest claimed: 2021-11-24 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Wei-Jen Wang; Yi Dao Wang; Tung Yao Lin - Web page: https://patentgrep.com/patent/US12218094B2 ## CPC - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser} - H10W 72/281: {Auxiliary members} - H10W 72/287: {Flow barriers} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer. ## Claims ### Claim 1 A method for manufacturing an electronic package structure, comprising: providing a first electronic component comprising a first conductive layer; performing a thermal treatment on the first electronic component without applying any laser energy on the first electronic component; and applying a laser energy on the first electronic component after performing the thermal treatment. ### Claim 2 (depends on 1) The method of claim 1, further comprising: providing a second conductive layer; and performing the thermal treatment on the first electronic component to joint the first conductive layer to the second conductive layer. ### Claim 3 (depends on 2) The method of claim 2, further comprising: applying a compression to cause the first conductive layer and the second conductive layer to press against each other. ### Claim 4 (depends on 3) The method of claim 3, wherein the thermal treatment is performed on the first electronic component during applying the compression. ### Claim 5 (depends on 3) The method of claim 3, wherein applying the compression comprises pressing a second electronic component including the second conductive layer. ### Claim 6 (depends on 5) The method of claim 5, wherein pressing the second electronic component is earlier than applying the laser energy on the first electronic component. ### Claim 7 (depends on 2) The method of claim 2, further comprising: providing a conductive bump having a recess; and disposing a portion of the first conductive layer within the recess. ### Claim 8 (depends on 7) The method of claim 7, wherein disposing the portion of the first conductive layer within the recess is earlier than performing the thermal treatment on the first electronic component. ### Claim 9 A method for manufacturing an electronic package structure, comprising: providing a first electronic component comprising a first conductive layer; providing a second conductive layer; partially jointing the first conductive layer to the second conductive layer; and applying a condensed energy on the first electronic component to enlarge a joint region formed by partially jointing the first conductive layer to the second conductive layer. ### Claim 10 (depends on 9) The method of claim 9, further comprising applying a compression on the first conductive layer and the second conductive layer. ### Claim 11 (depends on 10) The method of claim 10, further comprising performing a thermal treatment on the first electronic component to partially joint the first conductive layer to the second conductive layer. ### Claim 12 (depends on 10) The method of claim 10, further comprising: providing a second electronic component comprising the second conductive layer; and pressing the second electronic component to partially joint the first conductive layer to the second conductive layer. ### Claim 13 (depends on 12) The method of claim 12, wherein applying the condensed energy on the first electronic component is later than pressing the second electronic component. ### Claim 14 (depends on 9) The method of claim 9, further comprising applying the condensed energy to completely joint the first conductive layer to the second conductive layer. ### Claim 15 (depends on 9) The method of claim 9, wherein the condensed energy is configured to shrink or condense the second conductive layer. ### Claim 16 (depends on 15) The method of claim 15, further comprising forming a gap between the second conductive layer and an insulation layer. ### Claim 17 A method for manufacturing an electronic package structure, comprising: providing a first electronic component comprising a first conductive layer and a second electronic component comprising a second conductive layer contacting the first conductive layer; performing a thermal compression bonding process on the first electronic component and the second electronic component; and applying a condensed energy on the first electronic component. ### Claim 18 (depends on 17) The method of claim 17, wherein the thermal compression bonding process is configured to alleviate a warpage of the first electronic component. ### Claim 19 (depends on 17) The method of claim 17, wherein the thermal compression bonding process comprises pressing the second electronic component. ### Claim 20 (depends on 18) The method of claim 18, wherein the first electronic component comprises a first surface facing the second electronic component, the second electronic component comprises a second surface facing the first electronic component, an edge portion of the first surface of the first electronic component is separated from the second surface of the second electronic component by a first distance in a first direction substantially perpendicular to the second surface, a center portion of the first surface is separated from the second surface by a second distance different from the first distance in the first direction, and the thermal compression bonding process is configured to reduce a difference between the first distance and the second distance.