# US 12,218,093 B2 · Semiconductor die connection system and method

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- Number: US 12,218,093 B2
- Document ID: US12218093B2
- Status: Granted
- Kind: B2
- Application number: 18/332,990
- Filed: 2023-06-12
- Published: 2023-10-12
- Granted: 2025-02-04
- Earliest claimed: 2012-01-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Fa Chen; Chen-Hua Yu; Sen-Bor Jan
- Web page: https://patentgrep.com/patent/US12218093B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a first die with a first width over a second die with a second width, wherein the second width is larger than the first width;
a through via in a substrate of the first die, wherein the through via has a top surface coplanar with a top surface of the substrate of the first die, wherein the through via has a bottom surface within the first die;
an underfill material between the first die and the second die; and
an encapsulant extending along a surface of the underfill material and a surface of the second die.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the encapsulant comprises a molding compound material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the encapsulant has an edge in physical contact with a side surface of the second die.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the edge of the encapsulant is coplanar with the side surface of the second die.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the encapsulant has a top surface coplanar with a top surface of the first die.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a connector is between the first die and second die and surrounded by the underfill material.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the connector comprises a solder bump.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second die is a memory die.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first die is bonded to the second die with a copper-to-copper bonding structure.

### Claim 10

A semiconductor device comprising:
a first die over a second die;
a through via in a substrate of the first die;
an underfill material between the first die and the second die;
an encapsulant encapsulating the first die and extending along a surface of the underfill material and a surface of the second die; and
a solder bump over the first die and electrically coupled to the through via, wherein the through via has a top surface coplanar with a top surface of the substrate of the first die.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first die is smaller than the second die.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the encapsulant comprises a molding compound material.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the encapsulant has a sidewall in physical contact with a sidewall of the second die.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the sidewall of the encapsulant is coplanar with the sidewall of the second die.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the encapsulant has a surface coplanar with a surface of the first die.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein a connector is between the first die and second die and surrounded by the underfill material.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein the first die is bonded to the second die with a copper-to-copper bonding structure.

### Claim 18

A semiconductor device comprising:
a first die having a first width bonded to a second die having a second width, the first and second dies being bonded with a connector, the second width being larger than the first width;
a through via in a substrate of the first die;
an encapsulant contacting a surface of the second die and has an edge coplanar with a side surface of the second die;
a redistribution layer on a top surface of the first die, the redistribution layer being electrically coupled and physically contacting the through via;
a solder bump on and electrically coupled to the redistribution layer; and
a second substrate over the first die and bonded to the solder bump.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the connector is a copper-to-copper bonding structure.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, the connector is a solder bump.