# US 12,218,092 B2 · Semiconductor package and method of manufacturing semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,092 B2 - Document ID: US12218092B2 - Status: Granted - Kind: B2 - Application number: 17/690,270 - Filed: 2022-03-09 - Published: 2023-02-09 - Granted: 2025-02-04 - Earliest claimed: 2021-08-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Moonyong Jang - Web page: https://patentgrep.com/patent/US12218092B2 ## CPC - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/00: Package configurations - H10W 70/635: {Through-vias} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07252: {changes in structures or sizes} - H10W 72/221: {Structures or relative sizes} - H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/235: {of outermost layers of multilayered bumps, e.g. bump coating not being conformal on a bump core} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/20: Configurations of stacked chips - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip. ## Claims ### Claim 1 A semiconductor package comprising: a package substrate including wiring patterns provided respectively in a plurality of insulation layers, the package substrate having insertion holes extending from an upper surface of the package substrate in a thickness direction of the package substrate to expose portions of the wiring patterns in different insulation layers; a semiconductor chip disposed on the package substrate, the semiconductor chip having a first surface on which chip pads are formed; a plurality of connection pins provided on the chip pads, respectively, the plurality of connection pins extending through corresponding ones of the insertion holes and electrically connecting to the portions of the wiring patterns, respectively, that are exposed by the insertion holes; and a molding member provided on the package substrate to cover the semiconductor chip, wherein heights of the plurality of connection pins from the first surface of the semiconductor chip are greater than depths of the corresponding ones of the insertion holes from the upper surface of the package substrate such that the plurality of connection pins physically contact the portions of the wiring patterns that are exposed by the corresponding ones of the insertion holes, wherein each of the plurality of connection pins includes a connection pillar provided on the respective chip pad and extending from the first surface of the semiconductor chip and a metal bonding layer provided to cover an entire outer surface of the connection pillar, and wherein the metal bonding layers of the plurality of connection pins physically contact and form a thermo-compression bond with the portions of the wiring patterns, respectively, that are exposed by the insertion holes. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the wiring patterns include a first wiring pattern, a second wiring pattern, and a third wiring pattern stacked sequentially on one another, and wherein the insertion holes include a first insertion hole exposing a portion of the first wiring pattern, a second insertion hole exposing a portion of the second wiring pattern and a third insertion hole exposing a portion of the third wiring pattern. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the plurality of connection pins includes: a first connection pin in the first insertion hole and electrically connected to the portion of the first wiring pattern that is exposed by the first insertion hole; a second connection pin in the second insertion hole and electrically connected to the portion of the second wiring pattern that is exposed by the second insertion hole; and a third connection pin in the third insertion hole and electrically connected to the portion of the third wiring pattern that is exposed by the third insertion hole. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the first connection pin has a first height from the first surface of the semiconductor chip, the second connection pin has a second height from the first surface of the semiconductor chip, and the third connection pin has a third height from the first surface of the semiconductor chip, the second height is greater than the first height, and the third height is greater than the second height. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the metal bonding layer at least partially fills a space between the surface of the connection pillar and an inner surface of a corresponding insertion hole. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the metal bonding layer includes a metal material, the metal material has a lower melting point than a melting point of the connection pillar, and the metal material is in a solid state at room temperature. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein each of the insertion holes has a first diameter within a range of about 15 μm to about 150 μm, and each of the plurality of connection pins has a second diameter within a range of about 5 μm to about 95 μm, the first diameter being greater than the second diameter. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein a height of each of the plurality of connection pins from the first surface of the semiconductor chip is within a range of about 15 μm to about 300 μm. ### Claim 9 (depends on 1) The semiconductor package of claim 1, further comprising: dummy connection pillars provided in corner regions, respectively, of the first surface of the semiconductor chip, the dummy connection pillars contacting the upper surface of the package substrate. ### Claim 10 A semiconductor package comprising: a package substrate including a first wiring pattern, a second wiring pattern, and a third wiring pattern sequentially stacked from an upper surface of the package substrate, the package substrate having a first insertion hole, a second insertion hole, and a third insertion hole extending from the upper surface of the package substrate into the package substrate to expose portions of the first wiring pattern, the second wiring pattern, and the third wiring pattern in different insulation layers, respectively; a semiconductor chip disposed on the package substrate and having a first surface on which chip pads are formed; a plurality of connection pins provided on the chip pads, respectively, the plurality of connection pins including a first connection pin, a second connection pin, and a third connection pin extending through the first insertion hole, the second insertion hole, and the third insertion hole to electrically connect to the portions of the first wiring pattern, the second wiring pattern, and the third wiring pattern that are exposed by the first insertion hole, the second insertion hole, and the third insertion hole, respectively; and a molding member provided on the package substrate to cover the semiconductor chip, wherein each of the first insertion hole, the second insertion hole, and the third insertion hole has a first diameter within a range of about 15 μm to about 150 μm, and each of the first connection pin, the second connection pin and the third connection pin has a second diameter within a range of about 5 μm to about 95 μm, the first diameter being greater than the second diameter, wherein a first height of the first connection pin from the first surface of the semiconductor chip is greater than a first depth of the first insertion hole from the upper surface of the package substrate, such that the first connection pin physically contacts the portion of the first wiring pattern, a second height of the second connection pin from the first surface of the semiconductor chip is greater than a second depth of the second insertion hole from the upper surface of the package substrate, such that the second connection pin physically contacts the portion of the second wiring pattern, and a third height of the third connection pin from the first surface of the semiconductor chip is greater than a third depth of the third insertion hole from the upper surface of the package substrate, such that the third connection pin physically contacts the portion of the third wiring pattern, wherein each of the first connection pin, the second connection pin and the third connection pin includes a connection pillar provided on the respective chip pad and extending from the first surface of the semiconductor chip and a metal bonding layer provided to cover an entire outer surface of the connection pillar, and wherein the metal bonding layers of the plurality of connection pins physically contact and form a thermo-compression bond with the portions of the wiring patterns, respectively, that are exposed by the insertion holes. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the second height is greater than the first height, and the third height is greater than the second height. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein the metal bonding layer at least partially fills a space between the surface of the connection pillar and an inner surface of a corresponding insertion hole. ### Claim 13 (depends on 10) The semiconductor package of claim 10, wherein the metal bonding layer includes a metal material, the metal material has a lower melting point than a melting point of the connection pillar, and the metal material is in a solid state at room temperature. ### Claim 14 A semiconductor package comprising: a package substrate; a first semiconductor chip disposed on the package substrate, the first semiconductor chip having a first surface on which chip pads are formed; a plurality of connection pins provided on the chip pads of the first semiconductor chip, respectively; at least one support structure on an upper surface of the package substrate, the at least one support structure being spaced from the first semiconductor chip; a plurality of additional semiconductor chips stacked on the package substrate and supported by the at least one support structure; and a molding member provided on the upper surface of the package substrate to cover the first semiconductor chip, the at least one support structure and the plurality of additional semiconductor chips, wherein the package substrate includes wiring patterns provided respectively in a plurality of insulation layers and the package substrate has insertion holes extending from the upper surface of the package substrate into the package substrate to expose portions of the wiring patterns in different insulation layers, respectively, and wherein the plurality of connection pins extend through corresponding ones of the insertion holes to electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes, and wherein heights of the plurality of connection pins from the first surface of the semiconductor chip are greater than depths of the corresponding ones of the insertion holes from the upper surface of the package substrate such that the plurality of connection pins physically contact the portions of the wiring patterns that are exposed by the corresponding ones of the insertion holes, wherein each of the plurality of connection pins includes a connection pillar provided on the respective chip pad and extending from the first surface of the semiconductor chip and a metal bonding layer provided to cover an entire outer surface of the connection pillar, and wherein the metal bonding layers of the plurality of connection pins physically contact and form a thermo-compression bond with the portions of the wiring patterns, respectively, that are exposed by the insertion holes. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein each of the insertion holes has a first diameter within a range of about 15 μm to about 150 μm, and each of the plurality of connection pins has a second diameter within a range of about 5 μm to about 95 μm, the first diameter being greater than the second diameter. ### Claim 16 (depends on 14) The semiconductor package of claim 14, wherein the height of each of the plurality of connection pins from the first surface of the first semiconductor chip is within a range of about 15 μm to about 300 μm. ### Claim 17 (depends on 14) The semiconductor package of claim 14, wherein a height of each of the at least one support structure from the package substrate is a same height as a height of the first semiconductor chip. ### Claim 18 (depends on 14) The semiconductor package of claim 14, further comprising: conductive connection members connecting chip pads of the plurality of additional semiconductor chips to substrate pads of the package substrate respectively.