# US 12,218,090 B2 · Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

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- Number: US 12,218,090 B2
- Document ID: US12218090B2
- Status: Granted
- Kind: B2
- Application number: 17/562,944
- Filed: 2021-12-27
- Published: 2022-06-30
- Granted: 2025-02-04
- Earliest claimed: 2020-12-25
- Assignees: Yibu Semiconductor Co., Ltd.
- Applicants: Yibu Semiconductor Co., Ltd.
- Inventors: Weiping Li
- Web page: https://patentgrep.com/patent/US12218090B2

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 72/7408: {the auxiliary support including alignment aids}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/072: {of bump connectors}
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/874: {On different surfaces}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

## Claims

### Claim 1

A semiconductor packaging method, comprising:
providing at least one semiconductor device and a first carrier board, wherein each of the at least one semiconductor device respectively has an active surface and an opposing passive surface, the active surface is formed with connecting terminals, the passive surface is formed with a plurality of first alignment solder parts, and the first carrier board is formed with a plurality of second alignment solder parts respectively corresponding to the plurality of first alignment solder parts;
placing the at least one semiconductor device on the first carrier board such that the plurality of first alignment solder parts are substantially aligned with respective ones of the plurality of second alignment solder parts;
forming a plurality of alignment solder joints by soldering the plurality of first alignment solder parts to respective ones of the plurality of second alignment solder parts to align and fix the at least one semiconductor device to the first carrier board;
removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device;
forming a molded package body on a side of the second carrier board where the at least one semiconductor device is disposed, the molded package body encapsulating the at least one semiconductor device; and
removing the second carrier board to expose the connecting terminals.

### Claim 2 (depends on 1)

The semiconductor packaging method according to claim 1, wherein the at least one semiconductor device includes a plurality of semiconductor devices, and forming a plurality of alignment solder joints comprises: while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, pressing the active surfaces of the plurality of semiconductor devices with a leveling plate to keep the active surfaces of the semiconductor devices positioned in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.

### Claim 3 (depends on 1)

The semiconductor packaging method according to claim 1, wherein the at least one semiconductor device includes a plurality of semiconductor devices, the semiconductor packaging method further comprising, after forming the plurality of alignment solder joints and before removing the first carrier board, melting or partially melting the plurality of alignment solder joints, pressing a leveling plate on the active surfaces of the plurality of semiconductor devices to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.

### Claim 4 (depends on 1)

A semiconductor packaging method according to claim 1, further comprising, before removing the first carrier board, turning over as a whole the at least one semiconductor device together with the first carrier board and the second carrier board.

### Claim 5 (depends on 1)

A semiconductor packaging method according to claim 1, further comprising, after attaching a second carrier board to the active surface of the at least one semiconductor device and removing the first carrier board, and before forming the molded package body, turning over as a whole the at least one semiconductor device and the second carrier board.

### Claim 6 (depends on 1)

A semiconductor packaging method according to claim 1, further comprising, after forming the package body and before removing the second carrier board, turning over as a whole the molded package body encapsulating the at least one semiconductor device together with the second carrier board.

### Claim 7 (depends on 1)

A semiconductor packaging method according to claim 1, further comprising, after removing the second carrier board, sequentially forming an interconnect layer and external terminals on a surface of the molded package body where the connecting terminals are exposed, whereby the connecting terminals are electrically connected to the external terminals through the interconnect layer.

### Claim 8 (depends on 7)

A semiconductor packaging method according to claim 7, further comprising, before forming the interconnect layer and the external terminals, turning over as a whole the molded package body and at least one semiconductor device encapsulated in the molded package body.

### Claim 9 (depends on 7)

A semiconductor packaging method according to claim 7, further comprising: after the interconnect layer and the external terminals are formed, dicing the molded package body to obtain individual packages.

### Claim 10 (depends on 7)

A semiconductor packaging method according to claim 7, wherein the interconnect layer comprises a re-distribution layer and an under-bump metallization layer sequentially formed in a direction away from the connecting terminals.

### Claim 11 (depends on 1)

A semiconductor packaging method according to claim 1, wherein one of a respective first alignment solder part and a corresponding second alignment solder part is a solder bump, and the other of the respective first alignment solder part and the corresponding second alignment solder part is a solder pad or a solder bump.

### Claim 12 (depends on 11)

A semiconductor packaging method according to claim 11, wherein at least the first or second alignment solder parts are made of solder, and soldering is performed by melting the solder.

### Claim 13 (depends on 12)

A semiconductor packaging method according to claim 12, wherein providing at least one semiconductor device and a first carrier board includes applying viscous flux on the plurality of first alignment-solder parts and/or the plurality of second alignment solder parts, and wherein forming the plurality of solder joints includes turning over as a whole the at least one semiconductor device and the first carrier board before soldering the plurality of first alignment solder parts to respective ones of the plurality of second alignment solder parts.

### Claim 14 (depends on 12)

A semiconductor packaging method according to claim 12, further comprising, after forming the plurality of alignment solder joints, turning over as a whole the at least one semiconductor device and the first carrier board to enable the active surface to face downwards, and melting or partially melting the plurality of alignment solder joints again whereby the plurality of alignment solder joints are elongated by weight of the at least one semiconductor device, before cooling and solidifying the plurality of alignment solder joints again.

### Claim 15 (depends on 1)

A semiconductor packaging method according to claim 1, further comprising thinning the molded package body from a side near the passive surface of the at least one semiconductor device.

### Claim 16 (depends on 1)

A semiconductor packaging method according to claim 1, further comprising: removing portions of the plurality of alignment solder joints when the first carrier board is removed or after the first carrier board is removed.

### Claim 17 (depends on 1)

A semiconductor component made by the semiconductor packaging method according to claim 1.

### Claim 18 (depends on 17)

An electronic device comprising the semiconductor component of claim 17.