# US 12,218,089 B2 · Packaged semiconductor device and method of forming thereof

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- Number: US 12,218,089 B2
- Document ID: US12218089B2
- Status: Granted
- Kind: B2
- Application number: 18/153,847
- Filed: 2023-01-12
- Published: 2023-06-01
- Granted: 2025-02-04
- Earliest claimed: 2020-06-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; Kuo-Chung Yee; Chih-Hang Tung
- Web page: https://patentgrep.com/patent/US12218089B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/874: {On different surfaces}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/016: {Cleaning}
- H10W 80/041: {Thermally treating}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 80/732: {having shape changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/798: {between a chip and a stacked discrete passive device}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a first die, the first die comprising:
a first substrate;
a first interconnect structure on a first side of the first substrate; and
a first device layer on a second side of the first substrate;
a second die on the first die, the second die comprising:
a second substrate;
a second interconnect structure on a first side of the second substrate, the second interconnect structure comprising a first line, the first line having a first thickness; and
a power distribution network (PDN) layer on the second interconnect structure, a conductive line of the PDN layer having a second thickness, the second thickness being greater than the first thickness; and
a third die on the second die, the third die comprising:
a third substrate; and
a second device layer on a first side of the third substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a front-side redistribution structure over the first die;
an encapsulant under the front-side redistribution structure, the encapsulant encapsulating the first die, the second die, and the third die;
a back-side redistribution structure under the encapsulant and the third die; and
a through via coupled to the front-side redistribution structure and the back-side redistribution structure, the through via being encapsulated by the encapsulant.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a package substrate attached to the back-side redistribution structure, wherein the package substrate is coupled to the through via through the back-side redistribution structure.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further comprising a surface mount device attached to the front-side redistribution structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a package substrate attached to the third die; and
an encapsulant on the package substrate, the encapsulant encapsulating the first die, the second die, and the third die.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
an interposer attached to the third die;
a package component attached to the interposer; and
an encapsulant on the interposer, the encapsulant encapsulating the first die, the second die, the third die, and the package component.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the interposer comprises a plurality of through vias.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the interposer comprises a third interconnect structure.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, further comprising:
a package substrate under the interposer; and
a plurality of connectors coupling the interposer to the package substrate.

### Claim 10

A semiconductor device comprising:
a first die, the first die comprising:
a first substrate;
a first plurality of bonding pads over the first substrate, the first plurality of bonding pads having a first pitch;
a second die attached to the first die, the second die comprising:
a second substrate;
a first interconnect structure over an active side of the second substrate;
a second interconnect structure over a backside of the second substrate;
a power distribution network (PDN) structure over the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate;
a second plurality of bonding pads over the PDN structure, the second plurality of bonding pads bonded to the first plurality of bonding pads; and
a third plurality of bonding pads over the first interconnect structure, the third plurality of bonding pads having a second pitch, the second pitch being less than the first pitch; and
a third die attached to the second die, wherein the second die is between the first die and the third die, the third die comprising:
a third substrate; and
a fourth plurality of bonding pads over an active side of the third substrate, the fourth plurality of bonding pads bonded to the third plurality of bonding pads.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second die further comprises a power component layer over the PDN structure.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the third die further comprises a plurality of through vias embedded in the third substrate.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the third die further comprises a global interconnect over a back side of the third substrate.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, further comprising a fourth die attached to the third die, wherein the third die is between the second die and the fourth die.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the bonding of the fourth plurality of bonding pads to the third plurality of bonding pads comprises metal-metal bonds.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the bonding of the fourth plurality of bonding pads to the third plurality of bonding pads comprises solder regions.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a first bonding layer and a first plurality of bonding pads over a first wafer;
forming a second bonding layer and a second plurality of bonding pads over a first surface of a second wafer;
bonding the first wafer to the second wafer, the bonding comprising bonding the first bonding layer to the second bonding layer and bonding each bonding pad of the first plurality of bonding pads with a respective bonding pad of the second plurality of bonding pads;
forming a power distribution network (PDN) layer over a second surface of the second wafer, the second surface being opposite the first surface;
forming a third bonding layer and a third plurality of bonding pads over the PDN layer;
forming a fourth bonding layer and a fourth plurality of bonding pads over a third wafer; and
bonding the second wafer to the third wafer, the bonding comprising bonding the third bonding layer to the fourth bonding layer and bonding each bonding pad of the third plurality of bonding pads with a respective bonding pad of the fourth plurality of bonding pads.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a deep trench capacitor over the PDN layer before forming the third bonding layer.

### Claim 19 (depends on 17)

The method of claim 17, further comprising forming a voltage regulation circuit over the PDN layer before forming the third bonding layer.

### Claim 20 (depends on 17)

The method of claim 17, further comprising forming a metal-insulator-metal capacitor over the PDN layer before forming the third bonding layer.