# US 12,218,087 B2 · Semiconductor device with composite conductive features and method for fabricating the same

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- Number: US 12,218,087 B2
- Document ID: US12218087B2
- Status: Granted
- Kind: B2
- Application number: 18/598,167
- Filed: 2024-03-07
- Published: 2024-07-25
- Granted: 2025-02-04
- Earliest claimed: 2022-03-18
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Teng-Yen Huang
- Web page: https://patentgrep.com/patent/US12218087B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a first semiconductor structure comprising a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a protection liner, a graphene liner in the protection liner and a core conductor in the graphene liner, wherein top surfaces of the protection liner, the graphene liner and the core conductor are coplanar with each other; and
forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, two first conductive layers in the first connecting insulating layer, and a first porous layer between the two first conductive layers;
wherein a porosity of the first porous layer is between about 25% and about 100%.

### Claim 2 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein forming the first connecting structure comprises:
forming the first connecting insulating layer on the first semiconductor structure;
forming the two first conductive layers in the first connecting insulating layer and a first energy-removable layer between the two first conductive layers; and
performing an energy treatment to turn the first energy-removable layer into the first porous layer.

### Claim 3 (depends on 2)

The method for fabricating the semiconductor device of claim 2, wherein the energy-removable layer comprises a base material and a decomposable porogen material.

### Claim 4 (depends on 3)

The method for fabricating the semiconductor device of claim 3, wherein the base material comprises methylsilsesquioxane, low-dielectric materials, or silicon oxide.

### Claim 5 (depends on 4)

The method for fabricating the semiconductor device of claim 4, wherein an energy source of the energy treatment is heat, light, or a combination thereof.

### Claim 6 (depends on 5)

The method for fabricating the semiconductor device of claim 5, further comprising:
performing a bonding process to bond a second semiconductor structure to the first connecting structure;
wherein a temperature of the bonding process is between about 300° C. and about 450° C.

### Claim 7 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the at least one of the plurality of first composite conductive features is formed by:
forming the protection liner in a U-shaped profile to have a cavity, wherein the graphene liner is disposed in the cavity of the protection liner at a position that a bottom surface of the graphene liner is in contact with a bottom wall of the cavity of the protection liner; and
forming the graphene liner in a U-shaped profile to have a cavity, wherein the core conductor disposed in the cavity of the graphene liner at a position that a bottom surface of the graphene line is in contact with a bottom wall of the cavity of the graphene liner.

### Claim 8 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein forming first semiconductor structure further comprising:
forming a recess in a first insulating layer; and
forming the first composite conductive feature in the recess, such that the graphene liner is located in the recess of the first insulating layer.

### Claim 9 (depends on 8)

The method for fabricating the semiconductor device of claim 8, wherein top surfaces of the protection liner, the graphene liner, the core conductor, and the first insulating layer are coplanar with each other.

### Claim 10 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the graphene liner is formed between the protection liner and the core conductor, such that the protection liner and the core conductor are separated by the graphene liner.

### Claim 11 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the graphene liner is formed by a CVD process.

### Claim 12 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the protection liner, the graphene liner and the core conductor are made of different materials.