# US 12,218,086 B2 · Semiconductor package and method of manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,086 B2 - Document ID: US12218086B2 - Status: Granted - Kind: B2 - Application number: 17/716,054 - Filed: 2022-04-08 - Published: 2023-03-02 - Granted: 2025-02-04 - Earliest claimed: 2021-08-26 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yongbum Kwon; Unbyoung Kang - Web page: https://patentgrep.com/patent/US12218086B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 72/073: {of die-attach connectors} - H10W 20/033: {in openings in dielectrics} - H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks} - H10W 72/01921: {using local deposition} - H10W 72/01961: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951)} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semiconductor package includes bonding first the and second structures, such that a first bonding structure is directly bonded to a second bonding structure. The forming of the first structure includes; forming a blocking layer on a metallic material layer including a first portion covering a concaved portion of the metallic material layer and a second portion covering a non-concaved portion of the metallic material layer, performing a first planarization process to remove the second portion of the blocking layer while the first portion of the blocking layer remains, performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer, performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer and forming a recessed portion below an upper surface of the metallic material layer on the barrier layer while removing the barrier layer on the insulating layer. ## Claims ### Claim 1 A method of manufacturing a semiconductor package, the method comprising: preparing a semiconductor structure including a semiconductor layer and a through-via penetrating through the semiconductor layer; forming an insulating layer on the semiconductor structure; forming an opening in the insulating layer to expose an upper surface of the through-via; forming a barrier layer on the insulating layer to cover the upper surface of the through-via, inner side surfaces of the opening, and an upper surface of the insulating layer; forming a metallic material layer on the barrier layer, wherein the metallic material layer includes a concave portion and a non-concaved portion; forming a blocking layer on the metallic material layer, wherein the blocking layer includes a first portion covering the concaved portion of the metallic material layer and a second portion covering the non-concaved portion of the metallic material layer; performing a first planarization process to remove the second portion of the blocking layer, while the first portion of the blocking layer remains; performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer; and performing a wet etching process to remove the barrier layer on the insulating layer and the first portion of the blocking layer, wherein a recessed portion below an upper surface of the metallic material layer is formed in the barrier layer during the wet etching process. ### Claim 2 (depends on 1) The method of claim 1, wherein the barrier layer and the blocking layer includes a material having an etching selectivity with respect to the metal material layer and the insulating layer. ### Claim 3 (depends on 1) The method of claim 1, wherein the barrier layer on the insulating layer and the first portion of the blocking layer are simultaneously removed by the wet etching process. ### Claim 4 (depends on 1) The method of claim 1, wherein a portion of a side surface of the insulating layer and a side surface of the metallic material layer opposing the portion of the side surface of the insulating layer are exposed by the wet etching process. ### Claim 5 (depends on 1) The method of claim 1, wherein a depth of the recessed portion of the barrier layer is greater than or equal to a thickness of the barrier layer. ### Claim 6 (depends on 1) The method of claim 1, wherein the barrier layer has a thickness ranging from about 100 nm to about 200 nm, and a depth of the recessed portion of the barrier layer is about 300 nm or less. ### Claim 7 (depends on 1) The method of claim 1, wherein a portion of a surface of the metallic material layer below the first portion of the blocking layer is not exposed by the second planarization process. ### Claim 8 (depends on 1) The method of claim 1, wherein after performing the wet etching process, the barrier layer and the metallic material layer constitute a lower bonding pad, and the method further comprises: bonding a semiconductor chip including an upper bonding pad to the semiconductor structure by directly bonding the lower bonding pad and the upper bonding pad. ### Claim 9 (depends on 8) The method of claim 8, wherein the upper bonding pad includes an upper barrier layer and an upper metallic material layer, the upper metallic material layer and the metallic material layer of the lower bonding pad are directly bonded, and the upper barrier layer includes a portion recessed upwardly to be higher than a lower surface of the upper metallic material layer. ### Claim 10 (depends on 9) The method of claim 9, wherein the barrier layer of the lower bonding pad and the upper barrier layer of the upper bonding pad are spaced apart from each other. ### Claim 11 (depends on 1) The method of claim 1, wherein a surface of the non-concaved portion of the metallic material layer disposed on the insulating layer is exposed by the first planarization process. ### Claim 12 (depends on 1) The method of claim 1, wherein the insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer sequentially stacked on the semiconductor layer, the second insulating layer includes a second material different from a first material of the first insulating layer and different from a third material of the third insulating layer, and the first insulating layer includes a portion extending between the second insulating layer and a side surface of the through-via. ### Claim 13 (depends on 12) The method of claim 12, wherein the opening exposes the upper surface of the through-via, an upper surface of the first insulating layer, and an upper surface of the second insulating layer. ### Claim 14 A method of manufacturing a semiconductor package, the method comprising: forming a first structure including a first bonding structure including a first bonding pad; forming a second structure including a second bonding structure including a second bonding pad; and bonding the first structure and the second structure, such that the first bonding structure is directly bonded to the second bonding structure, wherein the forming of the first structure includes: preparing a semiconductor structure including a semiconductor layer and a through-via penetrating the semiconductor layer; forming an insulating layer on the semiconductor layer; forming an opening in the insulating layer exposing an upper surface of the through-via; forming a barrier layer on the insulating layer to cover the upper surface of the through-via, inner side surfaces of the opening and an upper surface of the insulating layer; forming a metallic material layer on the barrier layer, wherein the metallic material layer includes a concave portion and a non-concaved portion; forming a blocking layer on the metallic material layer, wherein the blocking layer includes a first portion covering the concaved portion of the metallic material layer and a second portion covering the non-concaved portion of the metallic material layer; performing a first planarization process to remove the second portion of the blocking layer, while the first portion of the blocking layer remains; performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer; performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer; and forming a recessed portion below an upper surface of the metallic material layer on the barrier layer while removing the barrier layer on the insulating layer. ### Claim 15 (depends on 14) The method of claim 14, wherein the barrier layer and the blocking layer include a material having an etching selectivity with respect to the metallic material layer and the insulating layer. ### Claim 16 (depends on 14) The method of claim 14, wherein the barrier layer and the blocking layer include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). ### Claim 17 (depends on 14) The method of claim 14, wherein a first processing time associated with the performing of the first planarization process is shorter than a second processing time associated with the performing of the second planarization process. ### Claim 18 (depends on 14) The method of claim 14, wherein the first bonding structure further includes a first bonding insulating layer surrounding at least a portion of a side surface of the first bonding pad, the second bonding structure further includes a second bonding insulating layer surrounding at least a portion of a side surface of the second bonding pad, the first bonding pad and the second bonding pad are directly bonded by copper-to-copper bonding, and the first bonding insulating layer and the second bonding insulating layer are directly bonded by dielectric-to-dielectric bonding. ### Claim 19 (depends on 14) The method of claim 14, wherein the bonding of the first structure and the second structure includes at least one of die-to-die bonding, die-to-wafer bonding, and wafer-to-wafer bonding. ### Claim 20 A method of manufacturing a semiconductor package, the method comprising: forming a first structure including a first bonding structure including a first bonding pad; forming a second structure including a second bonding structure including a second bonding pad; and bonding the first structure and the second structure, such that the first bonding structure is directly bonded to the second bonding structure, wherein at least one of the forming of the first structure and the forming of the second structure includes: preparing a semiconductor structure including a semiconductor layer and a through-via penetrating the semiconductor layer; forming an insulating layer on the semiconductor layer; forming an opening in the insulating layer exposing an upper surface of the through-via; forming a barrier layer on the insulating layer to cover the upper surface of the through-via, inner side surfaces of the opening and an upper surface of the insulating layer; forming a metallic material layer on the barrier layer, wherein the metallic material layer includes a concave portion and a non-concaved portion; forming a blocking layer on the metallic material layer, wherein the blocking layer includes a first portion covering the concaved portion of the metallic material layer and a second portion covering the non-concaved portion of the metallic material layer; performing a first planarization process to remove the second portion of the blocking layer, while the first portion of the blocking layer remains; performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer; performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer, a recessed portion is formed in the barrier layer while removing the barrier layer on the insulating layer, and a first recessed portion in a first barrier layer of the first bonding pad and a second recessed portion in a second barrier layer of the second bonding pad are respectively spaced apart from a bonding surface between the first bonding pad and the second bonding pad.