# US 12,218,083 B2 · Method of making an individualization zone of an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,083 B2 - Document ID: US12218083B2 - Status: Granted - Kind: B2 - Application number: 17/443,131 - Filed: 2021-07-21 - Published: 2022-01-27 - Granted: 2025-02-04 - Earliest claimed: 2020-07-22 - Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives - Applicants: Commissariat A L'energie Atomique Et Aux Energies Alternatives - Inventors: Nicolas Posseme; Stefan Landis; Hubert Teyssedre - Web page: https://patentgrep.com/patent/US12218083B2 ## CPC - H10W 20/43: Layouts of interconnections - H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering - G06F 21/44: Program or device authentication - G06F 21/73: by creating or determining hardware identification, e.g. serial numbers - H04L 9/3278: {using physically unclonable functions [PUF]} - H10P 50/73: {using masks for insulating materials} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H04L 2209/12: Details relating to cryptographic hardware or logic circuitry - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a conductor layer (30A) comprising via holes (30), the method comprising the following steps: providing at least one dielectric layer (200, 201, 202) having a thickness hd, forming a metal mask layer (300) having a thickness hm and a residual stress σr on the at least one dielectric layer (200, 201, 202), etching the layer (300) so as to form line patterns (310) of width l, etching the at least one dielectric layer (200, 201, 202) between the line patterns (310) so as to form trenches (210) separated by walls (211), filling the trenches (210) with an electrically conductive material so as to form the electrical tracks (10, 10KO) of the first level (10A), forming via holes (30, 30OK, 30KO1, 30KO2) of the conductor layer (30A), forming the second level (20A) of electrical tracks (20, 20OK), the method being characterized in that the thicknesses hd and hm, the residual stress σr, and the width l are chosen so that the line patterns (310) and the underlying walls (211) have random oscillations after etching of the at least one dielectric layer (200, 201, 202). ## Claims ### Claim 1 A method for making an individualization zone of a microelectronic chip, said chip comprising a first and a second level of electrical tracks, a level of interconnections located between the first and the second levels of electrical tracks and comprising vias to electrically connect electrical tracks of the first level to electrical tracks of the second level, the method comprising, in the individualization zone of the chip: providing a stack comprising at least one dielectric layer borne by a substrate with a metal mask layer above the stack, the at least one dielectric layer having a thickness hd and the metal mask layer having a thickness hm and a residual stress σr, etching the metal mask layer so as to form line patterns of width l organized according to a predefined arrangement plan, said line patterns to be transferred to the at least one dielectric layer, etching the at least one dielectric layer between the line patterns so as to form trenches separated by walls based on the at least one dielectric layer, filling the trenches with an electrically conductive material so as to form the electrical tracks of the first level, forming vias of the conductor layer according to the predefined arrangement plan, and forming the second level of electrical tracks, wherein the thicknesses hd and hm, the residual stress σr, and the width l are chosen so that the line patterns and the underlying walls have random oscillations after etching of the at least one dielectric layer the filling of the trenches being performed so that the electrical tracks of the first level are a function of these random oscillations, and the random oscillations being such that at least some of the vias are not connected to the electrical tracks of the first level. ### Claim 2 (depends on 1) The method according to claim 1, wherein the thickness hm of the metal mask layer is greater than 15 nm. ### Claim 3 (depends on 1) The method according to claim 1, wherein the thickness hd of the at least one dielectric layer is greater than 100 nm. ### Claim 4 (depends on 1) The method according to claim 1, wherein the metal mask layer is made of or based on one of Ti, TiN, and TaN. ### Claim 5 (depends on 1) The method according to claim 1, wherein the at least one dielectric layer comprises a layer based on dense SiOCH or porous SiOCH (p-SiOCH), or based on SiO2. ### Claim 6 (depends on 1) The method according to claim 1, wherein the second level of electrical tracks is formed in such a way that the electrical tracks of the second level have random oscillations. ### Claim 7 (depends on 1) The method according to claim 1, wherein the chip has at least one other zone, separate from the individualization zone to form a functional zone of the chip, said method further comprising: forming a protective mask in the individualization zone on the metal mask layer prior to said formation of the line patterns, etching the metal mask layer in the functional zone, outside the individualization zone, so that the metal mask layer in the functional zone has a thickness hf