# US 12,218,082 B2 · Package structure

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- Number: US 12,218,082 B2
- Document ID: US12218082B2
- Status: Granted
- Kind: B2
- Application number: 18/506,111
- Filed: 2023-11-09
- Published: 2024-02-29
- Granted: 2025-02-04
- Earliest claimed: 2021-07-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kai-Ming Chiang; Chao-wei Li; Wei-Lun Tsai; Chia-Min Lin; Yi-Da Tsai; Sheng-Feng Weng; Yu-Hao Chen; Sheng-Hsiang Chiu; Chih-Wei Lin; Ching-Hua Hsieh
- Web page: https://patentgrep.com/patent/US12218082B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

## Claims

### Claim 1

A structure, comprising:
a first semiconductor die comprising conductive terminals;
second semiconductor dies stacked over the first semiconductor die, the conductive terminals being spaced apart from the second semiconductor die by the first semiconductor die;
an insulating encapsulation disposed on the first semiconductor die to laterally encapsulate the second semiconductor die, sidewalls of the insulating encapsulation being substantially aligned with sidewalls of the first semiconductor die; and
a buffer cap encapsulating the conductive terminals, wherein the buffer cap covers the sidewalls of the first semiconductor die and the sidewalls of the insulating encapsulation, wherein a maximum height of the buffer cap substantially equals to a sum of a first height of the first semiconductor die, a second height of the second semiconductor dies, and a third height of the conductive terminals.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first semiconductor die is wider than the second semiconductor dies.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the buffer cap comprises:
a first buffer layer covering a first surface of the first semiconductor die, the sidewalls of the first semiconductor die and upper portions of the sidewalls of the insulating encapsulation; and
a second buffer layer covering bottom portions of the sidewalls of the insulating encapsulation, wherein sidewalls of the first buffer layer substantially align with sidewalls of the second buffer layer.

### Claim 4 (depends on 3)

The structure of claim 3, wherein the first buffer layer comprises:
a base portion covering the first surface of the first semiconductor die and laterally encapsulating the conductive terminals; and
a ring-shaped protruding portion extending from the base portion to cover the sidewalls of the first semiconductor die and the upper portions of the sidewalls of the insulating encapsulation.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the ring-shaped protruding portion comprises a convex surface or a concave surface in contact with the second buffer layer.

### Claim 6 (depends on 4)

The structure of claim 4, wherein the ring-shaped protruding portion comprises a flat surface in contact with the second buffer layer.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the buffer cap is spaced apart from the second semiconductor dies by the first semiconductor die and the insulating encapsulation.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the conductive terminals penetrate through the buffer cap.

### Claim 9 (depends on 1)

The structure of claim 1 further comprising:
an adhesion layer in contact with the second semiconductor dies, the insulating encapsulation and the buffer cap.

### Claim 10

A package structure, comprising:
an electronic device comprising conductive terminals;
a buffer cap covering sidewalls of the electronic device, the buffer cap extending over a surface of the electronic device on which the conductive terminals are distributed to laterally encapsulate the conductive terminals;
a first insulating encapsulation laterally encapsulating the electronic device and the buffer cap; and
an adhesion layer in contact with the electronic device and the buffer cap.

### Claim 11 (depends on 10)

The package structure of claim 10, wherein the electronic device comprises a semiconductor die having the conductive terminals.

### Claim 12 (depends on 10)

The package structure of claim 10, wherein the electronic device comprises a memory device, and the memory device comprises:
a base semiconductor die, the conductive terminals being disposed on a first surface of the base semiconductor die;
memory dies stacked over a second surface of the base semiconductor die, the second surface being opposite to the first surface; and
a second insulating encapsulation disposed on the second surface of the base semiconductor die and laterally encapsulating the memory dies, the buffer cap covering the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation, wherein the first insulating encapsulation is spaced apart from the second insulating encapsulation by the buffer cap.

### Claim 13 (depends on 12)

The package structure of claim 12, wherein the buffer cap comprises:
a first buffer layer in contact with the surface of the electronic device and upper portions of the sidewalls of the electronic device, wherein the first buffer layer comprises: a base portion covering the first surface of the base semiconductor die and laterally encapsulating the conductive terminals; and a ring-shaped protruding portion extending from the base portion to cover the sidewalls of the base semiconductor die and the upper portions of the sidewalls of the insulating encapsulation; and
a second buffer layer in contact with bottom portions of the sidewalls of the electronic device, wherein sidewalls of the first buffer layer substantially align with sidewalls of the second buffer layer.

### Claim 14 (depends on 13)

The package structure of claim 13, wherein the ring-shaped protruding portion comprises a rounded and convex surface or a rounded and concave surface in contact with the second buffer layer.

### Claim 15 (depends on 13)

The package structure of claim 13, wherein the ring-shaped protruding portion comprises a flat surface in contact with the second buffer layer.

### Claim 16 (depends on 13)

The package structure of claim 13, wherein the adhesion layer is
in contact with the electronic device and the second buffer layer of the buffer cap, and the adhesion layer is laterally encapsulated by the first insulating encapsulation.

### Claim 17 (depends on 10)

The package structure of claim 10 further comprising:
a redistribution circuit structure disposed on the buffer cap and the first insulating encapsulation and electrically connected to the conductive terminals of the electronic device.

### Claim 18

A structure, comprising:
a first semiconductor die comprising conductive terminals;
second semiconductor dies stacked over the first semiconductor die, wherein the conductive terminals are spaced apart from the second semiconductor die by the first semiconductor die, and the first semiconductor die is wider than the second semiconductor dies;
an insulating encapsulation disposed on the first semiconductor die to laterally encapsulate the second semiconductor die, sidewalls of the insulating encapsulation being substantially aligned with sidewalls of the first semiconductor die; and
a buffer cap laterally encapsulating the first semiconductor die and the insulating encapsulation, wherein the buffer cap is wider than the first semiconductor die, wherein the buffer cap comprises:
a first buffer layer covering a first surface of the first semiconductor die, the sidewalls of the first semiconductor die and upper portions of the sidewalls of the insulating encapsulation; and
a second buffer layer covering bottom portions of the sidewalls of the insulating encapsulation, wherein sidewalls of the first buffer layer substantially align with sidewalls of the second buffer layer.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the conductive terminals penetrate through the buffer cap.

### Claim 20 (depends on 18)

The structure of claim 18, wherein a maximum height of the buffer cap substantially equals to a sum of a first height of the first semiconductor die, a second height of the second semiconductor dies, and a third height of the conductive terminals.