# US 12,218,081 B2 · Microelectronic devices with a polysilicon structure above a staircase structure, and related methods

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,081 B2
- Document ID: US12218081B2
- Status: Granted
- Kind: B2
- Application number: 18/356,997
- Filed: 2023-07-21
- Published: 2023-11-09
- Granted: 2025-02-04
- Earliest claimed: 2019-11-05
- Assignees: Lodestar Licensing Group LLC
- Applicants: Lodestar Licensing Group, LLC
- Inventors: Jivaan Kishore Jhothiraman; John M. Meldrim; Lifang Xu
- Web page: https://patentgrep.com/patent/US12218081B2

## CPC

- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

## Claims

### Claim 1

A microelectronic device, comprising:
a stack structure comprising vertically repeated tiers individually comprising at least one conductive material and at least one insulative material, the stack structure defining at least one staircase structure with steps along horizontal edges of the tiers;
a polysilicon fill material substantially filling a volume above the at least one staircase structure, the polysilicon fill material substantially forming to the steps of the at least one staircase structure; and
a dielectric material between the polysilicon fill material and the at least one staircase structure.

### Claim 2 (depends on 1)

The microelectronic device of claim 1, wherein the stack structure comprises multiple staircase structures defined by the stack structure, the multiple staircase structures comprising a pair of opposing staircase structures each with the steps along the horizontal edges of the tiers.

### Claim 3 (depends on 2)

The microelectronic device of claim 2, wherein the volume above the at least one staircase structure, substantially filled by the polysilicon fill material, comprises:
a first portion above one of the pair of the opposing staircase structures; and
a second portion above another of the pair of the opposing staircase structures.

### Claim 4 (depends on 3)

The microelectronic device of claim 3, wherein the volume defines a height-to-width ratio of at least about 4:1.

### Claim 5 (depends on 1)

The microelectronic device of claim 1, further comprising a slit extending a vertical height of the polysilicon fill material and bordered by the polysilicon fill material.

### Claim 6 (depends on 5)

The microelectronic device of claim 5, further comprising an additional slit extending through the stack structure, the slit and the additional slit defining a block of the microelectronic device.

### Claim 7 (depends on 5)

The microelectronic device of claim 5, further comprising an additional slit extending through the stack structure, the slit being defined by sidewalls of the polysilicon fill material, the additional slit defined by sidewalls of the tiers of the stack structure.

### Claim 8 (depends on 1)

The microelectronic device of claim 1, further comprising at least one conductive contact structure extending through the polysilicon fill material to a base structure below the stack structure.

### Claim 9 (depends on 8)

The microelectronic device of claim 8, further comprising at least one additional conductive contact structure extending through the polysilicon fill material to at least one of the steps.

### Claim 10 (depends on 8)

The microelectronic device of claim 8, further comprising at least one support structure extending through the stack structure to the base structure.

### Claim 11 (depends on 1)

The microelectronic device of claim 1, wherein the vertically repeated tiers comprise vertically interleaved conductive structures and insulative structures, the conductive structures comprising the at least one conductive material, the insulative structures comprising the at least one insulative material.

### Claim 12 (depends on 1)

The microelectronic device of claim 1, wherein the stack structure comprises:
a lower deck comprising some of the tiers; and
an upper deck comprising some additional of the tiers, the upper deck being above the lower deck.

### Claim 13

A microelectronic device, comprising:
a stack structure comprising insulative structures and conductive structures, the insulative structures and the conductive structures arranged in tiers, the conductive structures providing steps of at least one staircase structure extending at least a portion of a height of the stack structure;
a dielectric liner substantially conforming to the steps of the at least one staircase structure; and
a polysilicon fill material substantially filling a volume above the dielectric liner and the at least one staircase structure, a lower boundary of the polysilicon fill material substantially conforming to an upper boundary of the dielectric liner.

### Claim 14 (depends on 13)

The microelectronic device of claim 13, wherein the at least one staircase structure comprises a pair of substantially mirrored staircase structures.

### Claim 15 (depends on 14)

The microelectronic device of claim 14, further comprising at least one slit extending through the polysilicon fill material between the pair of substantially mirrored staircase structures.

### Claim 16 (depends on 13)

The microelectronic device of claim 13, further comprising slits extending through the polysilicon fill material and through the stack structure to partition the stack structure into multiple blocks.

### Claim 17 (depends on 13)

The microelectronic device of claim 13, wherein the tiers individually comprise one of the insulative structures and one of the conductive structures.

### Claim 18

An electronic system, comprising:
a three-dimensional array of microelectronic devices, the three-dimensional array comprising:
a stack structure comprising a vertical sequence of tiers, the tiers individually comprising at least one conductive structure and at least one insulative structure, the stack structure defining at least one staircase with steps along horizontal ends of the conductive structures of the tiers;
a polysilicon fill material within a volume above and having boundaries partially defined by the at least one staircase;
a dielectric liner within the volume and between the polysilicon fill material and the at least one staircase, the dielectric liner substantially conforming to the steps of the at least one staircase;
at least one processor in operable communication with the three-dimensional array of microelectronic devices; and
at least one peripheral device in operable communication with the at least one processor.

### Claim 19 (depends on 18)

The electronic system of claim 18, wherein the polysilicon fill material defines a greater horizontal width at an upper elevation than at a lower elevation.

### Claim 20 (depends on 18)

The electronic system of claim 18, further comprising at least one conductive contact structure extending through a portion of the polysilicon fill material.