# US 12,218,078 B2 · Semiconductor memory device and manufacturing method of the semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,078 B2 - Document ID: US12218078B2 - Status: Granted - Kind: B2 - Application number: 17/713,869 - Filed: 2022-04-05 - Published: 2023-04-27 - Granted: 2025-02-04 - Earliest claimed: 2021-10-26 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jun Hyuk Park; Kyung Min Park; Sung Gon Jin; Dong Won Choi - Web page: https://patentgrep.com/patent/US12218078B2 ## CPC - H10B 43/10: characterised by the top-view layout - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 61/22: {of the field-effect transistor [FET] type} - H10B 63/34: {of the vertical channel field-effect transistor type} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked in a vertical direction; a dummy stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers, which are alternately stacked in the vertical direction, the dummy stack structure being disposed at a level at which the gate stack structure is disposed; a channel structure penetrating the gate stack structure; a memory layer disposed between each of the plurality of conductive patterns and the channel structure; and a dummy pillar penetrating a portion of the dummy stack structure with a length less than a length of the channel structure in the vertical direction. ## Claims ### Claim 1 A method of manufacturing a semiconductor memory device, the method comprising: forming a lower stack structure including a lower scribe region and a lower chip region; forming a lower hole penetrating the lower scribe region of the lower stack structure; forming, in the lower hole, a measurement pillar including a buried layer disposed at a lower portion of the lower hole, and a reflective metal layer and an etch stop layer, which are disposed at an upper portion of the lower hole; forming an upper stack structure on the lower stack structure to cover the measurement pillar; and forming an upper hole overlapping with the measurement pillar, the upper hole penetrating the upper stack structure, wherein a hardness of the buried layer is less than hardnesses of the reflective metal layer and the etch stop layer, and wherein the reflective metal layer is formed of a material having an atomic number greater than an atomic number of the etch stop layer. ### Claim 2 (depends on 1) The method of claim 1, further comprising, after the upper hole penetrating the upper stack structure is formed, measuring an overlay between the lower hole and the upper hole, based on a center point measured from the reflective metal layer of the measurement pillar. ### Claim 3 (depends on 1) The method of claim 1, wherein the lower chip region of the lower stack structure includes a cell array region and a connection region extending from the cell array region, wherein, while the lower hole is formed, a lower channel hole penetrating the cell array region of the lower stack structure and a dummy hole penetrating the connection region of the lower stack structure are formed, wherein, while the measurement pillar is formed, a sacrificial pillar disposed in the lower channel hole and a dummy pillar disposed in the dummy hole are formed, and wherein, while the upper hole is formed, an upper channel hole penetrating a portion of the upper stack structure overlapping with the sacrificial pillar is formed. ### Claim 4 (depends on 1) The method of claim 1, wherein the buried layer is formed of a carbon-based material. ### Claim 5 (depends on 1) The method of claim 1, wherein the reflective metal layer is formed of a material having an atomic number greater than 55. ### Claim 6 (depends on 5) The method of claim 5, wherein the reflective metal layer includes at least one of tantalum and tungsten. ### Claim 7 (depends on 1) The method of claim 1, wherein the etch stop layer includes a titanium nitride layer. ### Claim 8 (depends on 1) The method of claim 1, wherein the forming of the measurement pillar includes: forming the buried layer at the lower portion of the lower hole; forming the reflective metal layer on the buried layer; and forming the etch stop layer on the reflective metal layer. ### Claim 9 (depends on 1) The method of claim 1, wherein the forming of the measurement pillar includes: forming the buried layer at the lower portion of the lower hole; forming the etch stop layer extending along a surface of the buried layer and a sidewall of the upper portion of the lower hole; and forming the reflective metal layer on the etch stop layer to fill a central region of the upper portion of the lower hole. ### Claim 10 (depends on 1) The method of claim 1, wherein the forming of the measurement pillar includes: forming the buried layer at the lower portion of the lower hole; forming a liner pattern extending along a surface of the buried layer and a sidewall of the upper portion of the lower hole; forming the reflective metal layer along a surface of the liner pattern; and forming a core pattern on the reflective metal layer to fill a central region of the upper portion of the lower hole, and wherein each of the liner pattern and the core pattern is the etch stop layer.