# US 12,218,077 B2 · Semiconductor device package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,077 B2
- Document ID: US12218077B2
- Status: Granted
- Kind: B2
- Application number: 17/705,216
- Filed: 2022-03-25
- Published: 2023-09-28
- Granted: 2025-02-04
- Earliest claimed: 2022-03-25
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Cheng-Nan Lin; Ming-Chiang Lee; Yung-I Yeh
- Web page: https://patentgrep.com/patent/US12218077B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

## Claims

### Claim 1

A semiconductor device package, comprising:
a carrier;
a first electronic component disposed on the carrier;
a support component disposed on the carrier;
a second electronic component disposed on the first electronic component and supported by the support component,
wherein the second electronic component comprises a first set of conductive pads, and the support component and at least one of the first set of conductive pads are overlapping; and
a third electronic component disposed on the second electronic component, wherein the first set of conductive pads are not covered by the third electronic component.

### Claim 2 (depends on 1)

The semiconductor device package of claim 1, wherein the third electronic component comprises a second set of conductive pads, and the support component is overlapped by at least one of the second set of conductive pads vertically.

### Claim 3 (depends on 2)

The semiconductor device package of claim 2, wherein the first set of conductive pads and the second set of conductive pads are arranged along edges of the support component from a top view.

### Claim 4 (depends on 1)

The semiconductor device package of claim 1, wherein a lateral surface of the second electronic component and a lateral surface of the support component are substantially coplanar.

### Claim 5 (depends on 1)

The semiconductor device package of claim 1, wherein the second electronic component has an active surface and a second surface opposite to the active surface, the active surface is farther from the carrier than the second surface.

### Claim 6 (depends on 1)

The semiconductor device package of claim 1, wherein a roughness of a backside surface of the first electronic component is greater than a roughness of a lateral surface of the first electronic component.

### Claim 7

A semiconductor device package, comprising:
a first carrier;
a first electronic component disposed on the first carrier;
a conductive structure disposed on the first carrier;
a second carrier in contact with the conductive structure; and
a second electronic component disposed on the second carrier; and
a first conductive element extending along a lateral side of second electronic component and electrically connects the second electronic component to the second carrier,
wherein the second carrier comprises a conductive layer and a dielectric layer covering the conductive layer and contacting the first electronic component, and wherein a first portion of the conductive layer over the first electronic component is physically spaced apart from the first electronic component by the dielectric layer.

### Claim 8 (depends on 7)

The semiconductor device package of claim 7, further comprising:
a supporting component disposed between the first carrier and the second carrier, wherein a second portion of the conductive layer over the supporting component contacts the supporting component.

### Claim 9 (depends on 7)

The semiconductor device package of claim 7, wherein an end of the first conductive element is over the conductive structure.

### Claim 10 (depends on 9)

The semiconductor device package of claim 9, wherein a conductive layer in the second carrier electrically connects the end of the first conductive element to the conductive structure.

### Claim 11 (depends on 7)

The semiconductor device package of claim 7, further comprising:
a supporting component disposed between the first carrier and the second carrier; and
a first set of conductive structures arranged along a first edge of the support component;
wherein one of the first set of conductive structures supports an end of the first conductive element.

### Claim 12 (depends on 11)

The semiconductor device package of claim 11, further comprising:
a third electronic component disposed on the second electronic component; and
a second set of conductive structures arranged along a second edge of the support component substantially perpendicular to the first edge of the support component;
wherein one of the second set of conductive structures support an end of a second conductive element electrically connecting the third electronic component to the second carrier.

### Claim 13 (depends on 12)

The semiconductor device package of claim 12, further comprising:
a third set of conductive structures arranged along a first edge of the first electronic component substantially parallel to the first edge of the support component;
wherein the third set of conductive structures are not electrically connected to the second carrier and is configured to balance a copper coverage of the second carrier and to alleviate warpage.

### Claim 14 (depends on 13)

The semiconductor device package of claim 13, further comprising:
a fourth set of conductive structures arranged along a second edge of the first electronic component substantially parallel to the second edge of the support component;
wherein a part of the fourth set of conductive structures are not electrically connected with the second carrier and is configured to balance a copper coverage of the second carrier and to alleviate warpage.

### Claim 15

A semiconductor device package, comprising:
a first electronic component;
a second electronic component disposed on the first electronic component;
a conductive wire having a first end electrically connecting the second electronic component and a second end electrically connecting the first electronic component;
a support component supporting the first end; and
a plurality of conductive structures disposed along at least two edges of the first electronic component, and wherein at least one of the plurality of conductive structures is disposed at least partially under the second end.

### Claim 16 (depends on 15)

The semiconductor device package of claim 15, further comprising:
a carrier disposed between the first electronic component and the second electronic component;
wherein the second electronic component is attached to the carrier by an adhesive layer; and
wherein the conductive wire is electrically connected to at least one of the plurality of conductive structures by the carrier.