# US 12,218,075 B2 · Package structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,075 B2
- Document ID: US12218075B2
- Status: Granted
- Kind: B2
- Application number: 17/566,575
- Filed: 2021-12-30
- Published: 2023-07-06
- Granted: 2025-02-04
- Earliest claimed: 2021-12-30
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Cheng-Yuan Kung; Hsu-Chiang Shih; Hung-Yi Lin; Chien-Mei Huang
- Web page: https://patentgrep.com/patent/US12218075B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/10: Arrangements for heating
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 70/692: Ceramics or glasses
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/072: {of bump connectors}
- H10W 72/30: Die-attach connectors
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

## Claims

### Claim 1

A package structure, comprising:
an encapsulant;
a patterned circuit structure disposed on the encapsulant, and including a pad;
at least one electronic component disposed on the patterned circuit structure, and including a bump electrically connected to the pad; and
a shrinkage modifier encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation, wherein a coefficient of thermal expansion of the shrinkage modifier is less than a coefficient of thermal expansion of the patterned circuit structure and a coefficient of thermal expansion of the encapsulant.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the patterned circuit structure includes a die-bonding region, the electronic component is disposed on the die-bonding region, and the die-bonding region is at least partially located within a vertical projection region of the shrinkage modifier on the patterned circuit structure.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the patterned circuit structure includes a plurality of die-bonding regions, the at least one electronic component includes a plurality of electronic components each disposed in a respective one of the die-bonding regions, and the die-bonding regions are at least partially located within a vertical projection region of the shrinkage modifier on the patterned circuit structure.

### Claim 4 (depends on 3)

The package structure of claim 3, wherein a width of the shrinkage modifier is greater than a width of an extent covering all the die-boding regions.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein a heat transfer coefficient of the shrinkage modifier is greater than a heat transfer coefficient of the electronic component.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein a rigidity of the shrinkage modifier is greater than a rigidity of the electronic component.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the patterned circuit structure includes a die-bonding region, the electronic component is disposed on the die-bonding region, and a portion of the encapsulant is disposed between the patterned circuit structure and the shrinkage modifier, and located in a vertical projection region of the die-bonding region of the patterned circuit structure.

### Claim 8

A package structure, comprising:
an interposer;
a plurality of electronic components disposed above the interposer and electrically communicating with each other through the interposer; and
a decoupling structure electrically connected to the electronic components through the interposer, wherein the interposer has a power region and a bridge region, the electronic components electrically communicate with each other through the bridge region, and the decoupling structure is disposed closer to the power region than to the bridge region.

### Claim 9 (depends on 8)

The package structure of claim 8, wherein the bridge region is closer to a gap between two adjacent electronic components than the power region is.

### Claim 10 (depends on 9)

The package structure of claim 9, wherein the interposer comprises a plurality of conductive vias disposed in the power region and electrically connected to a same one of the electronic components.

### Claim 11 (depends on 9)

The package structure of claim 9, wherein the decoupling structure is at least partially located within a vertical projection region of the power region.

### Claim 12 (depends on 11)

The package structure of claim 11, wherein the decoupling structure is disposed under the interposer.

### Claim 13 (depends on 10)

The package structure of claim 10, wherein one of the electronic components has a circuit region and a power receiving region, the circuit region is adapted for communicating with the other of the electronic components, and the decoupling structure is disposed closer to the power receiving region than to the circuit region.

### Claim 14 (depends on 13)

The package structure of claim 13, wherein the decoupling structure is located within a vertical projection region of the power receiving region.

### Claim 15 (depends on 10)

The package structure of claim 10, wherein the electronic components comprise a first electronic component and a second electronic component disposed adjacent to the first electronic component, the first electronic component has a first surface facing the second electronic component and a second surface opposite to the first surface, and the decoupling structure is located within a vertical projection of the first electronic component and disposed closer to the second surface than to the first surface.

### Claim 16

A package structure, comprising:
an encapsulant having a bridge region, a power region around the bridge region, and a signal region around the power region;
a bridge interposer encapsulated in the encapsulant, and disposed in the bridge region and the power region of the encapsulant, wherein the bridge interposer comprises a first conductive structure disposed in the bridge region of the encapsulant and a second conductive structure disposed in the power region of the encapsulant, and a circuit density of the first conductive structure is greater than a circuit density of the second conductive structure; and
a plurality of conductive pillars disposed in the signal region of the encapsulant, wherein the circuit density of the second conductive structure is greater than a circuit density of the conductive pillars.

### Claim 17 (depends on 16)

The package structure of claim 16, wherein a line width of the first conductive structure is less than a line width of the second conductive structure, and the line width of the second conductive structure is less than a width of one of the conductive pillars.

### Claim 18 (depends on 16)

The package structure of claim 16, further comprising a plurality of electronic components, disposed on the encapsulant and located within a vertical projection of the bridge region and the power region of the encapsulant.