# US 12,218,074 B2 · DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,074 B2 - Document ID: US12218074B2 - Status: Granted - Kind: B2 - Application number: 18/332,047 - Filed: 2023-06-09 - Published: 2023-10-05 - Granted: 2025-02-04 - Earliest claimed: 2018-06-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Harry-Hak-Lay Chuang; Tien-Wei Chiang; Kuo-An Liu; Chia-Hsiang Chen - Web page: https://patentgrep.com/patent/US12218074B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - H10N 50/01: Manufacture or treatment - H10N 50/80: Constructional details - H10W 42/287: {materials for magnetic shielding, e.g. ferromagnetic materials} - H10W 70/429: {being the outer leads} - H10W 72/50: Bond wires - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers. ## Claims ### Claim 1 An integrated chip, comprising: a chip comprising a semiconductor device; and a shielding structure abutting the chip, wherein the shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip, wherein the first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers, wherein the first dielectric layer is disposed between the two or more metal layers. ### Claim 2 (depends on 1) The integrated chip of claim 1, wherein the first dielectric layer and the two or more metal layers are vertically stacked with one another, wherein the two or more metal layers respectively have an area greater than that of the first horizontal surface of the chip. ### Claim 3 (depends on 1) The integrated chip of claim 1, wherein the first dielectric layer is disposed laterally between the two or more metal layers, wherein bottom surfaces of the two or more metal layers are coplanar with a bottom surface of the first dielectric layer. ### Claim 4 (depends on 3) The integrated chip of claim 3, wherein the two or more metal layers each have a width less than a width of the first horizontal surface of the chip. ### Claim 5 (depends on 4) The integrated chip of claim 4, wherein the two or more metal layers each have a length greater than a length of the first horizontal surface of the chip. ### Claim 6 (depends on 1) The integrated chip of claim 1, wherein the first dielectric layer has a plurality of first elongated segments intersecting a plurality of second elongated segments, wherein the two or more metal layers are spaced apart from one another by at least one individual elongated segment in the first or second elongated segments. ### Claim 7 (depends on 1) The integrated chip of claim 1, wherein the shielding structure comprises a second horizontal region adjacent to a second horizontal surface of the chip opposite the first horizontal surface, wherein the second horizontal region comprises a second multilayer structure comprising a second dielectric layer and two or more other metal layers. ### Claim 8 (depends on 7) The integrated chip of claim 7, wherein the shielding structure comprises a vertical structure disposed on opposite sides of a first pair of opposing sidewalls of the chip, wherein the vertical structure extends continuously between the first and second multilayer structures. ### Claim 9 (depends on 8) The integrated chip of claim 8, wherein the vertical structure comprises a third multilayer structure configured as the first multilayer structure or the second multilayer structure. ### Claim 10 (depends on 8) The integrated chip of claim 8, wherein the vertical structure is disposed on opposite sides of a second pair of opposing sidewalls of the chip, wherein the second pair of opposing sidewalls continuously extend between the first pair of opposing sidewalls. ### Claim 11 An integrated chip, comprising: a semiconductor structure having a first lateral surface opposite a second lateral surface and a pair of sidewalls extending between the first and second lateral surfaces; and a housing structure comprising a first lateral region, a second lateral region, and a sidewall region extending between the first and second lateral regions, wherein the semiconductor structure is spaced vertically between the first and second lateral regions, and wherein the housing structure comprises a shielding stack comprising a plurality of metal structures and an insulating structure spacing the metal structures from one another. ### Claim 12 (depends on 11) The integrated chip of claim 11, wherein the semiconductor structure comprises a memory cell. ### Claim 13 (depends on 11) The integrated chip of claim 11, wherein the first and second lateral regions respectively comprise the shielding stack, wherein in top view an area of the shielding stack is greater than areas of the first and second lateral surfaces. ### Claim 14 (depends on 13) The integrated chip of claim 13, wherein the sidewall region comprises a support structure extending vertically from the first lateral region to the second lateral region. ### Claim 15 (depends on 13) The integrated chip of claim 13, wherein the sidewall region comprises the shielding stack. ### Claim 16 (depends on 11) The integrated chip of claim 11, wherein the sidewall region comprise openings vertically aligned with the pair of sidewalls of the semiconductor structure, wherein conductive wires extend from outside the housing structure through the openings towards the pair of sidewalls of the semiconductor structure, wherein the conductive wires are electrically coupled to the semiconductor structure. ### Claim 17 A method for forming an integrated chip, comprising: forming a first multilayer structure comprising a first metal layer and a first dielectric layer; trimming the first multilayer structure to meet dimensions of a first outer surface of a package structure, wherein the package structure comprises a chip; and attaching the first multilayer structure to the first outer surface of the package structure. ### Claim 18 (depends on 17) The method of claim 17, further comprising: forming a second multilayer structure comprising a second metal layer and a second dielectric layer; trimming the second multilayer structure to meet dimensions of a second outer surface of the package structure; and attaching the second multilayer structure to the second outer surface of the package structure. ### Claim 19 (depends on 17) The method of claim 17, wherein the first multilayer structure comprises a second metal layer disposed on the first dielectric layer. ### Claim 20 (depends on 19) The method of claim 19, wherein an adhesive material is disposed between the first dielectric layer and the first and second metal layers.