# US 12,218,071 B2 · Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,071 B2 - Document ID: US12218071B2 - Status: Granted - Kind: B2 - Application number: 18/208,785 - Filed: 2023-06-12 - Published: 2023-10-12 - Granted: 2025-02-04 - Earliest claimed: 2021-07-13 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Srinivas V. Pietambaram; Sri Ranga Sai Boyapati; Robert A. May; Kristof Darmawikarta; Javier Soto Gonzalez; Kwangmo Lim - Web page: https://patentgrep.com/patent/US12218071B2 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/90: Bond pads, in general - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/9413: {on encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/10: Configurations of laterally-adjacent chips - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed. ## Claims ### Claim 1 A package, comprising: a die having a plurality of die pads; a molding layer laterally surrounding the die and the plurality of die pads, the molding layer having an uppermost surface at a same level as an uppermost surface of the plurality of die pads; a plurality of conductive vias, wherein individual ones of the plurality of conductive vias are on a corresponding one of the plurality of die pads, each of the plurality of conductive vias having an uppermost surface, wherein the uppermost surface of each of the conductive vias is vertically overlapping with the corresponding one of the die pads; and a plurality of conductive traces on the uppermost surface of the molding layer over the die, the plurality of conductive traces having an uppermost surface below the uppermost surface of each of the plurality of conductive vias. ### Claim 2 (depends on 1) The package of claim 1, further comprising: a dielectric layer above the die and the molding layer, the dielectric layer over the plurality of conductive traces, and the dielectric layer having an uppermost surface at a same level as the uppermost surface of the plurality of conductive vias. ### Claim 3 (depends on 2) The package of claim 2, further comprising: an adhesion layer between the molding layer and the dielectric layer, and the adhesion layer between the plurality of die pads and the dielectric layer. ### Claim 4 (depends on 3) The package of claim 3, wherein the adhesion layer is along sidewalls of the plurality of conductive vias. ### Claim 5 (depends on 3) The package of claim 3, wherein the adhesion layer has an uppermost surface at a same level as the uppermost surface of the plurality of conductive vias. ### Claim 6 (depends on 3) The package of claim 3, wherein the adhesion layer comprises silicon and nitrogen. ### Claim 7 (depends on 3) The package of claim 3, wherein the adhesion layer has a sidewall in alignment with a sidewall of the molding layer. ### Claim 8 (depends on 3) The package of claim 3, wherein the dielectric layer has a sidewall in alignment with a sidewall of the molding layer, and wherein the adhesion layer has a sidewall in alignment with the sidewall of the molding layer. ### Claim 9 (depends on 2) The package of claim 2, wherein the dielectric layer has a sidewall in alignment with a sidewall of the molding layer. ### Claim 10 (depends on 1) The package of claim 1, wherein the plurality of conductive vias has a bottommost surface at a same level as a bottommost surface of the plurality of conductive traces. ### Claim 11 A package, comprising: a first die having a first plurality of die pads; a second die having a second plurality of die pads, the second die laterally spaced apart from the first die; a molding layer laterally surrounding the first die, the second die, the first plurality of die pads and the second plurality of die pads, the molding layer having an uppermost surface at a same level as an uppermost surface of the first plurality of die pads and the second plurality of die pads; a first plurality of conductive vias, wherein individual ones of the first plurality of conductive vias are on a corresponding one of the first plurality of die pads, the first plurality of conductive vias having an uppermost surface; a second plurality of conductive vias, wherein individual ones of the second plurality of conductive vias are on a corresponding one of the second plurality of die pads, the second plurality of conductive vias having an uppermost surface, wherein one of the second plurality of conductive vias is electrically coupled to one of the first plurality of conductive vias; a first plurality of conductive traces on the uppermost surface of the molding layer over the first die, the first plurality of conductive traces having an uppermost surface below the uppermost surface of the first plurality of conductive vias; and a second plurality of conductive traces on the uppermost surface of the molding layer over the second die, the second plurality of conductive traces having an uppermost surface below the uppermost surface of the second plurality of conductive vias. ### Claim 12 (depends on 11) The package of claim 11, further comprising: a dielectric layer above the first die, the second die and the molding layer, the dielectric layer over the first plurality of conductive traces and the second plurality of conductive traces, and the dielectric layer having an uppermost surface at a same level as the uppermost surface of the first plurality of conductive vias and the second plurality of conductive vias. ### Claim 13 (depends on 12) The package of claim 12, wherein the dielectric layer has a sidewall in alignment with a sidewall of the molding layer. ### Claim 14 (depends on 12) The package of claim 12, further comprising: an adhesion layer between the molding layer and the dielectric layer, the adhesion layer between the first plurality of die pads and the dielectric layer, and the adhesion layer between the second plurality of die pads and the dielectric layer. ### Claim 15 (depends on 14) The package of claim 14, wherein the adhesion layer is along sidewalls of the first plurality of conductive vias and the second plurality of conductive vias. ### Claim 16 (depends on 14) The package of claim 14, wherein the adhesion layer has an uppermost surface at a same level as the uppermost surface of the first plurality of conductive vias and the second plurality of conductive vias. ### Claim 17 (depends on 14) The package of claim 14, wherein the adhesion layer comprises silicon and nitrogen. ### Claim 18 (depends on 14) The package of claim 14, wherein the adhesion layer has a sidewall in alignment with a sidewall of the molding layer. ### Claim 19 (depends on 14) The package of claim 14, wherein the dielectric layer has a sidewall in alignment with a sidewall of the molding layer, and wherein the adhesion layer has a sidewall in alignment with the sidewall of the molding layer. ### Claim 20 (depends on 11) The package of claim 11, wherein the first plurality of conductive vias has a bottommost surface at a same level as a bottommost surface of the first plurality of conductive traces, and the second plurality of conductive vias has a bottommost surface at a same level as a bottommost surface of the second plurality of conductive traces. ### Claim 21 A package, comprising: a die having a plurality of die pads; a molding layer laterally surrounding the die and the plurality of die pads, the molding layer having an uppermost surface at a same level as an uppermost surface of the plurality of die pads; a plurality of conductive vias, wherein individual ones of the plurality of conductive vias are on a corresponding one of the plurality of die pads, the plurality of conductive vias having an uppermost surface; a plurality of conductive traces on the uppermost surface of the molding layer over the die, the plurality of conductive traces having an uppermost surface below the uppermost surface of the plurality of conductive vias; and a dielectric layer above the die and the molding layer, the dielectric layer over the plurality of conductive traces, and the dielectric layer having an uppermost surface at a same level as the uppermost surface of the plurality of conductive vias. ### Claim 22 (depends on 21) The package of claim 21, further comprising: an adhesion layer between the molding layer and the dielectric layer, and the adhesion layer between the plurality of die pads and the dielectric layer. ### Claim 23 (depends on 22) The package of claim 22, wherein the adhesion layer is along sidewalls of the plurality of conductive vias. ### Claim 24 (depends on 22) The package of claim 22, wherein the adhesion layer has an uppermost surface at a same level as the uppermost surface of the plurality of conductive vias. ### Claim 25 (depends on 22) The package of claim 22, wherein the adhesion layer comprises silicon and nitrogen. ### Claim 26 (depends on 22) The package of claim 22, wherein the adhesion layer has a sidewall in alignment with a sidewall of the molding layer. ### Claim 27 (depends on 22) The package of claim 22, wherein the dielectric layer has a sidewall in alignment with a sidewall of the molding layer, and wherein the adhesion layer has a sidewall in alignment with the sidewall of the molding layer. ### Claim 28 (depends on 21) The package of claim 21, wherein the dielectric layer has a sidewall in alignment with a sidewall of the molding layer.