# US 12,218,070 B2 · Semiconductor package and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,070 B2 - Document ID: US12218070B2 - Status: Granted - Kind: B2 - Application number: 18/133,656 - Filed: 2023-04-12 - Published: 2023-08-03 - Granted: 2025-02-04 - Earliest claimed: 2018-02-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hae-Jung Yu; Kyung Suk Oh - Web page: https://patentgrep.com/patent/US12218070B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 72/90: Bond pads, in general - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 70/63: Vias, e.g. via plugs - H10W 70/655: Fan-out layouts - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals. ## Claims ### Claim 1 A semiconductor package, comprising: a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including first redistribution pads on the first surface and first vias below the first redistribution pads; a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including an active surface facing the redistribution layer, a first side surface, and a second side surface opposite the first side surface; a wiring substrate on the second surface of the redistribution layer and surrounding the semiconductor chip, the wiring substrate including base layers and conductive structures in the base layers, the conductive structures being spaced apart from the semiconductor chip, and each of the conductive structures including a conductive pad at one end; a molding member encapsulating the semiconductor chip, contacting side surfaces of the wiring substrate, and having openings exposing the conductive pads; and external connection terminals on and contacting the conductive pads of the conductive structures, wherein the conductive pads are arranged according to a first separation distance, and the first redistribution pads are arranged according to a second separation distance, wherein the second separation distance is smaller than the first separation distance, wherein the first separation distance is defined as a distance between a pair of adjacent ones of the conductive pads positioned closer to the second side surface than to the first side surface of the semiconductor chip, wherein upper surfaces of the first vias are at the same vertical level as the first surface of the redistribution layer, and wherein each of the first redistribution pads contacts a corresponding one of the first vias. ### Claim 2 (depends on 1) The package as claimed in claim 1, wherein the semiconductor chip further includes a programmable chip. ### Claim 3 (depends on 1) The package as claimed in claim 1, wherein the redistribution layer further includes second redistribution pads on the first surface thereof, the second redistribution pads having a pitch different from a pitch of the first redistribution pads. ### Claim 4 (depends on 1) The package as claimed in claim 1, wherein, when viewed in a plan view, at least one of the first redistribution pads is spaced apart from the semiconductor chip. ### Claim 5 (depends on 1) The package as claimed in claim 1, further comprising a first semiconductor device on the first surface of the redistribution layer, the first semiconductor device being coupled to the first redistribution pads. ### Claim 6 (depends on 5) The package as claimed in claim 5, wherein the first semiconductor device and the semiconductor chip are connected to each other via the redistribution layer and the first redistribution pads on the first surface of the redistribution layer, and wherein all the first redistribution pads are in a region overlapped by the first semiconductor device and the semiconductor chip. ### Claim 7 (depends on 5) The package as claimed in claim 5, wherein the redistribution layer further includes second redistribution pads on the first surface thereof, the second redistribution pads having a pitch different from a pitch of the first redistribution pads. ### Claim 8 (depends on 1) The package as claimed in claim 1, wherein at least some of the first redistribution pads are coupled to the external connection terminals through the redistribution layer and the conductive structures. ### Claim 9 (depends on 1) The package as claimed in claim 1, further comprising: a hole penetrating the base layers of the wiring substrate, the semiconductor chip being inside the hole. ### Claim 10 (depends on 1) The package as claimed in claim 1, wherein the external connection terminals have a non-overlapping relationship with the semiconductor chip, and wherein, in a top view, a pitch of the first redistribution pads is smaller than a pitch of the external connection terminals. ### Claim 11 (depends on 1) The package as claimed in claim 1, wherein the external connection terminals are arranged around a perimeter of the semiconductor chip and horizontally spaced apart from the semiconductor chip. ### Claim 12 (depends on 1) The package as claimed in claim 1, wherein the first redistribution pads and the semiconductor chip have a non-overlapping relationship. ### Claim 13 (depends on 1) The package as claimed in claim 1, wherein the second separation distance is defined as a distance between a pair of adjacent ones of the first redistribution pads. ### Claim 14 A semiconductor package, comprising: a redistribution layer having a first surface and a second surface opposite to each other and including first redistribution pads on the first surface of the redistribution layer and first vias below the first redistribution pads; a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including chip pads facing the redistribution layer; conductive structures on the second surface of the redistribution layer and spaced apart from the semiconductor chip, each of the conductive structures including a conductive pad at one end; and a first semiconductor device on the first surface of the redistribution layer, the first semiconductor device including connection pads facing the redistribution layer, wherein the first redistribution pads are connected to the connection pads, respectively, wherein the conductive pads are arranged according to a first separation distance, wherein the first redistribution pads are arranged according to a second separation distance smaller than the first separation distance, and wherein the first redistribution pads do not overlap the semiconductor chip in a vertical direction, wherein the semiconductor chip includes first and second side surfaces opposite to each other, the first separation distance being defined as a distance between a pair of adjacent ones of the conductive pads positioned closer to the second side surface than to the first side surface of the semiconductor chip, wherein upper surfaces of the first vias are at the same vertical level as the first surface of the redistribution layer, and wherein each of the first redistribution pads contacts a corresponding one of the first vias. ### Claim 15 (depends on 14) The package as claimed in claim 14, further comprising: a second semiconductor device on the first surface of the redistribution layer, wherein the second semiconductor device has a height different from a height of the first semiconductor device. ### Claim 16 (depends on 15) The package as claimed in claim 15, wherein, when viewed in a plan view, at least a portion of the first semiconductor device does not overlap the semiconductor chip. ### Claim 17 (depends on 15) The package as claimed in claim 15, wherein the first semiconductor device further includes: a package substrate, the semiconductor chip being on the package substrate; and a molding member on the package substrate and covering the semiconductor chip. ### Claim 18 A semiconductor package, comprising: a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including first redistribution pads on the first surface; a first semiconductor device on the first surface of the redistribution layer, the first semiconductor device being coupled to the first redistribution pads; a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including an active surface facing the redistribution layer, a first side surface, and a second side surface opposite the first side surface; a wiring substrate on the second surface of the redistribution layer and surrounding the semiconductor chip, the wiring substrate including a base layer and conductive structures, the conductive structures being spaced apart from the semiconductor chip, and each of the conductive structures including a conductive pad at one end; and external connection terminals on and coupled to the conductive pads of the conductive structures, wherein the conductive pads are arranged according to a first separation distance, and the first redistribution pads are arranged according to a second separation distance smaller than the first separation distance, wherein the first separation distance is defined as a distance between a pair of adjacent ones of the conductive pads positioned closer to the second side surface than to the first side surface of the semiconductor chip, wherein the second separation distance is defined as a distance between a pair of adjacent ones of the first redistribution pads, wherein the first semiconductor device and the semiconductor chip are connected to each other via the redistribution layer and the first redistribution pads on the first surface of the redistribution layer, and wherein all the first redistribution pads are in a region overlapped by the first semiconductor device. ### Claim 19 (depends on 18) The package as claimed in claim 18, wherein the redistribution layer further includes second redistribution pads on the first surface thereof, and wherein the second redistribution pads have a pitch different from a pitch of the first redistribution pads.