# US 12,218,069 B2 · Multi-chip package with high density interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,069 B2 - Document ID: US12218069B2 - Status: Granted - Kind: B2 - Application number: 18/091,781 - Filed: 2022-12-30 - Published: 2023-05-04 - Granted: 2025-02-04 - Earliest claimed: 2020-06-17 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Aleksandar Aleksov; Adel A. Elsherbini; Kristof Darmawikarta; Robert A. May; Sri Ranga Sai Boyapati - Web page: https://patentgrep.com/patent/US12218069B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/63: Vias, e.g. via plugs - H10W 70/635: {Through-vias} - H10W 72/0198: {batch processes} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07252: {changes in structures or sizes} - H10W 72/07254: {changes in dispositions} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed. ## Claims ### Claim 1 A system, comprising: a multi-chip package, comprising: a substrate having a top side opposite a bottom side, the substrate having a lateral width; a first die coupled to the top side of the substrate by a first plurality of contacts; a second die coupled to the top side of the substrate by a second plurality of contacts, the second die laterally spaced apart from the first die, and the second die having a thickness different than a thickness of the first die; a first plurality of interconnects in the substrate, the first plurality of interconnects comprising horizontal portions and vertical portions; a second plurality of interconnects in the substrate, the second plurality of interconnects comprising a first interconnect in a first sub-surface layer of the substrate and coupling an outermost contact of the first plurality of contacts to an outermost contact of the second plurality of contacts, and the second plurality of interconnects comprising a second interconnect in a second sub-surface layer of the substrate, the second sub-surface layer beneath the first sub-surface layer, and the second interconnect coupling a next outermost contact of the first plurality of contacts to a next outermost contact of the second plurality of contacts; and a mold compound laterally adjacent to and between the first die and the second die; an interposer having a top side opposite a bottom side, wherein the bottom side of the substrate of the multi-chip package is coupled to the top side of the interposer, and wherein the interposer has a lateral width greater than the lateral width of the substrate; and a printed circuit board having a top side opposite a bottom side, wherein the bottom side of the interposer is coupled to the top side of the printed circuit board. ### Claim 2 (depends on 1) The system of claim 1, wherein the substrate comprises multiple organic layers. ### Claim 3 (depends on 1) The system of claim 1, wherein the second die is a die stack. ### Claim 4 (depends on 1) The system of claim 1, wherein the second plurality of interconnects does not extend through the substrate. ### Claim 5 (depends on 1) The system of claim 1, wherein the mold compound extends to edges of the substrate. ### Claim 6 (depends on 1) The system of claim 1, wherein the second plurality of interconnects comprise a third interconnect in a third sub-surface layer of the substrate, the third sub-surface layer beneath the second sub-surface layer, and the third interconnect coupling a next to next outermost contact of the first plurality of contacts to a next to next outermost contact of the second plurality of contacts. ### Claim 7 (depends on 6) The system of claim 6, wherein the second plurality of interconnects comprise a fourth interconnect in a fourth sub-surface layer of the substrate, the fourth sub-surface layer beneath the third sub-surface layer, and the fourth interconnect coupling a next to next to next outermost contact of the first plurality of contacts to a next to next to next outermost contact of the second plurality of contacts. ### Claim 8 (depends on 1) The system of claim 1, wherein the first plurality of interconnects has a pitch less than a pitch of interconnects in the interposer. ### Claim 9 A system, comprising: a multi-chip package, comprising: a substrate having a top side opposite a bottom side, the substrate having a lateral width; a die coupled to the top side of the substrate by a first plurality of contacts; a die stack coupled to the top side of the substrate by a second plurality of contacts, the die stack laterally spaced apart from the die, and the die stack having a bottommost die having a thickness different than a thickness of the die; a first interconnect extending through the substrate; a second interconnect in a first sub-surface layer of the substrate, wherein the second interconnect does not extend through the substrate, the second interconnect coupling an outermost contact of the first plurality of contacts to an outermost contact of the second plurality of contacts from a cross-sectional perspective; a third interconnect in a second sub-surface layer of the substrate, the second sub-surface layer beneath the first sub-surface layer, wherein the third interconnect does not extend through the substrate, and the third interconnect coupling a next outermost contact of the first plurality of contacts to a next outermost contact of the second plurality of contacts from the cross-sectional perspective; a fourth interconnect in a third sub-surface layer of the substrate, the third sub-surface layer beneath the second sub-surface layer, wherein the fourth interconnect does not extend through the substrate, and the fourth interconnect coupling a next to next outermost contact of the first plurality of contacts to a next to next outermost contact of the second plurality of contacts from the cross-sectional perspective; and a mold compound laterally adjacent to and between the die and the second die; and an interposer having a top side opposite a bottom side, wherein the bottom side of the substrate of the multi-chip package is coupled to the top side of the interposer, and wherein the interposer has a lateral width greater than the lateral width of the substrate. ### Claim 10 (depends on 9) The system of claim 9, wherein the substrate comprises multiple organic layers, and wherein the mold compound extends to edges of the substrate. ### Claim 11 (depends on 9) The system of claim 9, further comprising a fifth interconnect in a fourth sub-surface layer of the substrate, the fourth sub-surface layer beneath the third sub-surface layer, wherein the fourth interconnect does not extend through the substrate, and the fourth interconnect coupling a next to next to next outermost contact of the first plurality of contacts to a next to next to next outermost contact of the second plurality of contacts. ### Claim 12 (depends on 9) The system of claim 9, wherein the first plurality of interconnects has a pitch less than a pitch of interconnects in the interposer. ### Claim 13 A method of fabricating a system, the method comprising: forming a multi-chip package, comprising: a substrate having a top side opposite a bottom side, the substrate having a lateral width; a first die coupled to the top side of the substrate by a first plurality of contacts; a second die coupled to the top side of the substrate by a second plurality of contacts, the second die laterally spaced apart from the first die, and the second die having a thickness different than a thickness of the first die; a first plurality of interconnects in the substrate, the first plurality of interconnects comprising horizontal portions and vertical portions; a second plurality of interconnects in the substrate, the second plurality of interconnects comprising a first interconnect in a first sub-surface layer of the substrate and coupling an outermost contact of the first plurality of contacts to an outermost contact of the second plurality of contacts, and the second plurality of interconnects comprising a second interconnect in a second sub-surface layer of the substrate, the second sub-surface layer beneath the first sub-surface layer, and the second interconnect coupling a next outermost contact of the first plurality of contacts to a next outermost contact of the second plurality of contacts; and a mold compound laterally adjacent to and between the first die and the second die; coupling an interposer to the substrate, the interposer having a top side opposite a bottom side, wherein the bottom side of the substrate of the multi-chip package is coupled to the top side of the interposer, and wherein the interposer has a lateral width greater than the lateral width of the substrate; and coupling a printed circuit board to the interposer, the printed circuit board having a top side opposite a bottom side, wherein the bottom side of the interposer is coupled to the top side of the printed circuit board. ### Claim 14 (depends on 13) The method of claim 13, wherein the substrate comprises multiple organic layers. ### Claim 15 (depends on 13) The method of claim 13, wherein the second die is a die stack. ### Claim 16 (depends on 13) The method of claim 13, wherein the second plurality of interconnects does not extend through the substrate. ### Claim 17 (depends on 13) The method of claim 13, wherein the mold compound extends to edges of the substrate. ### Claim 18 (depends on 13) The method of claim 13, wherein the second plurality of interconnects comprise a third interconnect in a third sub-surface layer of the substrate, the third sub-surface layer beneath the second sub-surface layer, and the second interconnect coupling a next to next outermost contact of the first plurality of contacts to a next to next outermost contact of the second plurality of contacts. ### Claim 19 (depends on 18) The method of claim 18, wherein the second plurality of interconnects comprise a fourth interconnect in a fourth sub-surface layer of the substrate, the fourth sub-surface layer beneath the third sub-surface layer, and the second interconnect coupling a next to next to next outermost contact of the first plurality of contacts to a next to next to next outermost contact of the second plurality of contacts. ### Claim 20 (depends on 13) The method of claim 13, wherein the first plurality of interconnects has a pitch less than a pitch of interconnects in the interposer.