Semiconductor package including adhesive layer and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYeohoon Yoon, Ilho Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package may include a first semiconductor chip, a second semiconductor chip spaced apart from the first semiconductor chip, an adhesive layer including an interposition portion and a side portion, and a molding layer. The molding layer may surround the first semiconductor chip, the second semiconductor chip, and the adhesive layer. The interposition portion may be between the first and second semiconductor chips. The side portion may contact a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. A top surface of the side portion is curved, and an outer side surface of the side portion is flat.
Claims19
A semiconductor package comprising:
- a base structure;
- a first semiconductor chip spaced apart from the base structure;
- a second semiconductor chip spaced apart from the first semiconductor chip;
- an adhesive layer including an interposition portion and a side portion,
- the interposition portion between the first semiconductor chip and the second semiconductor chip, the side portion contacting a side surface of the first semiconductor chip and a side surface of the second semiconductor chip,
- a top surface of the side portion being curved, and an outer side surface of the side portion being flat;
- and
- a molding layer surrounding the first semiconductor chip, the second semiconductor chip, and the adhesive layer, wherein
- the outer side surface of the side portion is coplanar with a side surface of the base structure.
A semiconductor package comprising:
- a base structure;
- a first bump connected to the base structure;
- a first semiconductor chip connected to the first bump;
- an adhesive layer including a first interposition portion and a side portion, the first interposition portion between the base structure and the first semiconductor chip, and the side portion contacting a top surface of the base structure and a side surface of the first semiconductor chip;
- and
- a molding layer surrounding the base structure, the first semiconductor chip, and the adhesive layer,
- a level of a bottom surface of the molding layer being equal to a level of a bottom surface of the base structure.
A semiconductor package comprising:
- semiconductor chips overlapping each other, the semiconductor chips including an uppermost semiconductor chip;
- an adhesive layer including interposition portions and a side portion,
- the interposition portions between the semiconductor chips, and
- the side portion connected to the interposition portions, and
- a level of a top surface of the side portion of the adhesive layer gradually increases as the top surface of the side portion of the adhesive layer extends from a side surface of the uppermost semiconductor chip to an uppermost portion of the side portion of the adhesive layer;
- and
- a molding layer surrounding the semiconductor chips and the adhesive layer.
Dependencies are inferred from the claim text.