# US 12,218,063 B2 · EMIB architecture with dedicated metal layers for improving power delivery

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- Number: US 12,218,063 B2
- Document ID: US12218063B2
- Status: Granted
- Kind: B2
- Application number: 16/810,192
- Filed: 2020-03-05
- Published: 2021-09-09
- Granted: 2025-02-04
- Earliest claimed: 2020-03-05
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jianyong Xie; Sujit Sharan; Huang-Ta Chen
- Web page: https://patentgrep.com/patent/US12218063B2

## CPC

- H10W 44/00: Electrical arrangements for controlling or matching impedance
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.

## Claims

### Claim 1

A bridge, comprising:
a silicon substrate;
a routing stack over the silicon substrate, wherein the routing stack comprises:
a first routing layer, wherein the first routing layer has a first thickness;
a second routing layer, wherein the second routing layer has a second thickness that is greater than the first thickness; and
a third routing layer having the first thickness, wherein the second routing layer is vertically between the first routing layer and the third routing layer.

### Claim 2 (depends on 1)

The bridge of claim 1, wherein the second routing layer comprises a plurality of sub-layers, wherein individual ones of the sub-layers have thicknesses between 1 μm and 4 μm.

### Claim 3 (depends on 1)

The bridge of claim 1, wherein there are at least four first routing layers.

### Claim 4 (depends on 1)

The bridge of claim 1, wherein the second thickness is at least twice the first thickness.

### Claim 5 (depends on 1)

The bridge of claim 1, wherein the second thickness is approximately 4 μm or greater.

### Claim 6 (depends on 1)

The bridge of claim 1, wherein the first routing layer is between the second routing layer and the silicon substrate.

### Claim 7 (depends on 1)

The bridge of claim 1, further comprising:
a plurality of pads over the routing stack.

### Claim 8 (depends on 7)

The bridge of claim 7, wherein a first pad of the plurality of pads is electrically coupled to the second routing layer by a first via, and a second pad of the plurality of pads is electrically coupled to the second routing layer by a second via, and wherein the first pad is electrically coupled to the second pad by a path comprising the first via, the second routing layer, and the second via.

### Claim 9 (depends on 8)

The bridge of claim 8, wherein a third pad of the plurality of pads is positioned between the first pad and the second pad.

### Claim 10 (depends on 1)

The bridge of claim 1, wherein the second routing layer comprises a first segment and a second segment, and wherein the first segment is electrically isolated from the second segment.

### Claim 11 (depends on 1)

The bridge of claim 1, wherein the second routing layer is a mesh.

### Claim 12

An electronic package, comprising:
a package substrate;
a bridge embedded in the package substrate, wherein the bridge comprises:
a silicon substrate;
a routing stack over the silicon substrate, wherein the routing stack comprises a first routing layer with a first thickness and a second routing layer with a second thickness and a third routing layer with the first thickness, wherein the second thickness is greater than the first thickness, and wherein the second routing layer is vertically between the first routing layer and the third routing layer;
a first die electrically coupled to the bridge; and
a second die electrically coupled to the bridge, wherein the first die is electrically coupled to the second die by the first routing layer.

### Claim 13 (depends on 12)

The electronic package of claim 12, further comprising a first power rail for the first die.

### Claim 14 (depends on 13)

The electronic package of claim 13, wherein the second routing layer is part of the first power rail.

### Claim 15 (depends on 14)

The electronic package of claim 14, wherein the first power rail includes a metal layer in the first die.

### Claim 16 (depends on 14)

The electronic package of claim 14, wherein the first power rail feeds power to a plurality of bumps that connect the first die to the bridge.

### Claim 17 (depends on 16)

The electronic package of claim 16, wherein individual ones of the plurality of bumps are electrically coupled to the second routing layer by a via in the routing stack.

### Claim 18 (depends on 12)

The electronic package of claim 12 wherein the second routing layer comprises a first segment for a first power rail and a second segment for a second power rail.

### Claim 19 (depends on 12)

The electronic package of claim 12, wherein the first die is a processor die, and wherein the second die is a memory die.

### Claim 20 (depends on 12)

The electronic package of claim 12, wherein the routing stack comprises at least four first routing layers.

### Claim 21 (depends on 20)

The electronic package of claim 20, further comprising:
a capacitor on the bridge, wherein a first electrode of the capacitor is the second routing layer and a second electrode of the capacitor is one of the reference layers.

### Claim 22

An electronic system, comprising:
a board;
a package substrate attached to the board;
a bridge embedded in the package substrate, wherein the bridge comprises at least five routing layers above a silicon substrate, and wherein at least one of the routing layers has a first thickness that is greater than a second thickness of other routing layers, the at least one of the routing layers vertically between a first one and a second one of the other routing layers;
a first die coupled to the bridge; and
a second die coupled to the bridge, wherein the first die is electrically coupled to the second die by one or more of the routing layers.

### Claim 23 (depends on 22)

The electronic system of claim 22, wherein a power rail for the first die comprises at least a portion of the routing layer with the first thickness.