# US 12,218,062 B2 · Method of fabricating a semiconductor memory device including an extension gate cutting region

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- Number: US 12,218,062 B2
- Document ID: US12218062B2
- Status: Granted
- Kind: B2
- Application number: 18/514,716
- Filed: 2023-11-20
- Published: 2024-03-14
- Granted: 2025-02-04
- Earliest claimed: 2020-01-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jun Hyoung Kim; Young-Jin Kwon; Geun Won Lim
- Web page: https://patentgrep.com/patent/US12218062B2

## CPC

- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10B 43/10: characterised by the top-view layout
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

## Claims

### Claim 1

A method of fabricating a semiconductor memory device, comprising:
providing a substrate including a cell array region and an extension region, which are arranged along a first direction, the extension region including contact regions and through regions, which are alternately arranged along the first direction;
forming a mold structure including first insulating patterns and second insulating patterns, which are alternately stacked on the substrate;
forming a channel structure through the mold structure of the cell array region to intersect the first insulating patterns and the second insulating patterns;
forming an extension gate cutting region extending in the first direction to cut the mold structure, in the mold structure of the contact regions; and
selectively removing the second insulating patterns in the contact regions, using the extension gate cutting region, so that the second insulating patterns in the through regions remain.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
after the selectively removing the second insulating patterns in the contact regions, forming gate electrodes in regions from which the second insulating patterns are removed.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the mold structure including the first insulating patterns and the second insulating patterns includes:
forming first insulating films and second insulating films, which are alternately stacked on the substrate; and
patterning the first insulating films and the second insulating films in the extension region in a stepwise fashion.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a cell gate cutting region extending in the first direction to cut the mold structure, in the mold structure of the cell array region.

### Claim 5 (depends on 4)

The method of claim 4, wherein the forming the cell gate cutting region and the forming the extension gate cutting region are performed at the same time.

### Claim 6

A method of fabricating a semiconductor memory device, comprising:
providing a substrate including a cell array region and an extension region, which are arranged along a first direction, the extension region including contact regions and through regions, which are alternately arranged along the first direction;
forming a mold structure including first insulating patterns and second insulating patterns, which are stacked on the substrate;
forming a channel structure through the mold structure of the cell array region to intersect the first insulating patterns and the second insulating patterns;
forming an extension gate cutting region extending in the first direction to cut the mold structure, in the mold structure of the contact regions; and
forming a cell gate cutting trench by removing a portion of first insulating patterns and second insulating patterns, in the mold structure of the cell array region, forming gate electrodes by filling the cell gate cutting trench with a semiconductor material.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the mold structure including the first insulating patterns and the second insulating patterns includes:
forming first insulating films and second insulating films, which are alternately stacked on the substrate; and
patterning the first insulating films and the second insulating films in the extension region in a stepwise fashion along the first direction.

### Claim 8 (depends on 7)

The method of claim 7, wherein patterning the first insulating films and the second insulating films includes:
forming exposed gate electrodes such that the exposed gate electrodes in the through region is longer than the exposed gate electrode in the contact regions.

### Claim 9 (depends on 6)

The method of claim 6, further comprising:
forming a plurality of through via in the through regions to penetrate first insulating patterns and second insulating patterns.

### Claim 10 (depends on 6)

The method of claim 6, further comprising:
forming gate contacts which are connected to gate electrodes, on the mold structure of contact regions.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming interlayer insulating films covering an upper surface of the mold structure of the extension region such that interlayer insulating films are penetrated by respective gate contacts.

### Claim 12 (depends on 6)

The method of claim 6, wherein forming the channel structure includes:
forming semiconductor patterns through the mold structure to connect with the substrate; and
forming information storage films to be interposed between semiconductor patterns and gate electrodes.

### Claim 13 (depends on 6)

The method of claim 6, further comprising:
forming a bitline extending in a second direction, which intersects the first direction, on the mold structure to be connected to the channel structure.