# US 12,218,057 B2 · Integrated circuit with backside interconnections and method of making same

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- Number: US 12,218,057 B2
- Document ID: US12218057B2
- Status: Granted
- Kind: B2
- Application number: 17/241,785
- Filed: 2021-04-27
- Published: 2022-10-27
- Granted: 2025-02-04
- Earliest claimed: 2021-04-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Wei Peng; Te-Hsin Chiu; Wei-An Lai; Ching-Wei Tsai; Jiann-Tyng Tzeng
- Web page: https://patentgrep.com/patent/US12218057B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3452: {Microstructure}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

## Claims

### Claim 1

A device, comprising:
a first transistor having a first drain region;
a second transistor having a second drain region, the first transistor and the second transistor being in an active layer of an integrated circuit; and
a first interconnect structure on a backside of the active layer, the first interconnect structure comprising:
a first backside contact electrically connected to the first drain region,
a second backside contact electrically connected to the second drain region, and
a backside interconnect directly connected to a sidewall of the first backside contact and a sidewall of the second backside contact, wherein the backside interconnect is a continuous structure, wherein a first distance from the first drain region to a distal end of the first backside contact from the first drain region is greater than a second distance from the first drain region to a distal end of the backside interconnect from the second drain region.

### Claim 2 (depends on 1)

The device of claim 1, further comprising
at least one backside power rail electrically connected to one of the first backside contact and the second backside contact; and
a second interconnect structure electrically connected to the first transistor and to a topside power rail on an opposite side of the active layer from the first interconnect structure.

### Claim 3 (depends on 2)

The device of claim 2, further comprising an insulating layer between the first interconnect structure and a layer containing the first transistor and the second transistor, wherein the insulating layer comprises a spacer.

### Claim 4 (depends on 3)

The device of claim 3, wherein the backside interconnect of the first interconnect structure electrically connects to the first backside contact and the second backside contact at a same side of the backside interconnect.

### Claim 5 (depends on 3)

The device of claim 3, wherein the backside interconnect of the first interconnect structure electrically connects to the first backside contact and the second backside contact at opposite sides of the backside interconnect.

### Claim 6 (depends on 2)

The device of claim 2, wherein the first interconnect structure comprises a backside via which electrically connects a backside power rail of the at least one backside power rail to a topside power rail of the at least one topside power rail.

### Claim 7 (depends on 2)

The device of claim 2, wherein the first interconnect structure further comprises a backside VDD rail and a backside VSS rail.

### Claim 8 (depends on 2)

The device of claim 2, wherein the second interconnect structure electrically connects a first source region of the first transistor to the topside power rail.

### Claim 9

A transmission gate of an integrated circuit, comprising:
a first P-type transistor and a second P-type transistor in an active layer;
a first N-type transistor and a second N-type transistor in the active layer;
a top interconnect on a first side of the active layer; and
a backside interconnect on a second side of the active layer opposite from the first side of the active layer, wherein
the top interconnect electrically connects a gate electrode of the first P-type transistor to a gate electrode of the second N-type transistor,
the backside interconnect continuously electrically connects a gate electrode of the second P type transistor to a gate electrode of the first N-type transistor;
a first backside contact electrically connected to the backside interconnect and the gate electrode of the second P-type transistor; and
a second backside contact electrically connected to the backside interconnect and the gate electrode of the first N-type transistor, wherein a first distance from the gate electrode of second P-type transistor to a distal end of the first backside contact from the gate electrode of the second P-type transistor is greater than a second distance from the gate electrode of the second P-type transistor to a distal end of the backside interconnect from the gate electrode of the first N-type transistor.

### Claim 10 (depends on 9)

The transmission gate of claim 9, wherein the first P-type transistor and the second P type transistor are electrically connected to the backside interconnect.

### Claim 11 (depends on 10)

The transmission gate of claim 10, wherein the backside interconnect is on an opposite side of a substrate from the top interconnect.

### Claim 12

A device, comprising:
a first transistor having a first drain region in a substrate and a first gate electrode;
a second transistor having a second drain region, the first transistor and the second transistor being in an active layer of an integrated circuit;
a first interconnect structure on a backside of the active layer, wherein the first interconnect structure comprises:
a first backside contact electrically connected to the first drain region,
a second backside contact electrically connected to the second drain region, and
a first backside interconnect directly connected to a sidewall of the first backside contact, wherein a first distance from the first drain region to a distal end of the first backside contact from the first drain region is greater than a second distance from the first drain region to a distal end of the backside interconnect from the second drain region; and
a second interconnect structure on the backside of the active layer, wherein the second interconnect structure comprises:
a third backside contact electrically connected to the first gate electrode; and
a third interconnect structure on a frontside of the active layer, wherein the third interconnect structure comprises:
a first frontside contact extending through the substrate, wherein the first frontside contact electrically connects the third interconnect structure to the second gate electrode.

### Claim 13 (depends on 12)

The device of claim 12, wherein the second transistor comprises a second gate electrode.

### Claim 14 (depends on 12)

The device of claim 12, wherein the second backside contact electrically connects the second drain region to a backside power rail.

### Claim 15 (depends on 12)

The device of claim 12, further comprising:
a backside power rail; and
an isolation plug, wherein the isolation plug is between the first backside contact and the backside power rail.

### Claim 16 (depends on 12)

The device of claim 12, wherein at least one of the first backside contact or the second backside contact extends into the active layer.

### Claim 17 (depends on 12)

The device of claim 12, wherein at least one of the first transistor or the second transistor comprises a gate all around (GAA) transistor.

### Claim 18 (depends on 12)

The device of claim 12, further comprising an insulation layer between the first backside interconnect and the second backside contact.

### Claim 19 (depends on 12)

The device of claim 12, further comprising:
a backside power rail; and
an isolation plug, wherein the isolation plug is between the third backside contact and the backside power rail.

### Claim 20 (depends on 12)

The device of claim 12, further comprising:
a second backside interconnect electrically connected to a sidewall of the third backside contact.