# US 12,218,055 B2 · Semiconductor device structure with conductive contacts of different widths and method for preparing the same

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- Number: US 12,218,055 B2
- Document ID: US12218055B2
- Status: Granted
- Kind: B2
- Application number: 18/635,387
- Filed: 2024-04-15
- Published: 2024-08-01
- Granted: 2025-02-04
- Earliest claimed: 2021-07-28
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ming-Hung Hsieh
- Web page: https://patentgrep.com/patent/US12218055B2

## CPC

- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10P 14/414: {of metal-silicide materials}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/049: {by diffusing alloying elements}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/065: {by making at least a portion of the conductive part non-conductive, e.g. by oxidation}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device structure with conductive contact of different widths and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact.

## Claims

### Claim 1

A method for preparing a semiconductor device structure, comprising:
forming a sacrificial layer over a semiconductor substrate;
forming a first opening and a second opening penetrating through the sacrificial layer, wherein a first width of the first opening is different from a second width of the second opening;
filling the first opening and the second opening with a first metal pillar and a second metal pillar;
removing the sacrificial layer after the first metal pillar and the second metal pillar are formed; and
reducing a width of the first metal pillar and a width of the second metal pillar after the sacrificial layer is removed.

### Claim 2 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein the width of the first metal pillar is reduced by performing an oxidation process, such that a portion of the metal pillar is transformed into a metal oxide layer.

### Claim 3 (depends on 2)

The method for preparing a semiconductor device structure of claim 2, wherein the metal oxide layer covers a top surface and sidewalls of a remaining portion of the first metal pillar.

### Claim 4 (depends on 3)

The method for preparing a semiconductor device structure of claim 3, further comprising:
forming a dielectric layer covering the metal oxide layer; and
performing a planarization process to expose the remaining portion of the first metal pillar.

### Claim 5 (depends on 3)

The method for preparing a semiconductor device structure of claim 3, further comprising:
removing the metal oxide layer to expose the remaining portion of the first metal pillar;
forming a dielectric layer covering the remaining portion of the first metal pillar; and
performing a planarization process to expose the remaining portion of the first metal pillar.