# US 12,218,052 B2 · Advanced lithography and self-assembled devices

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- Number: US 12,218,052 B2
- Document ID: US12218052B2
- Status: Granted
- Kind: B2
- Application number: 18/384,582
- Filed: 2023-10-27
- Published: 2024-02-29
- Granted: 2025-02-04
- Earliest claimed: 2020-12-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Richard E. Schenker; Robert L Bristol; Kevin L. Lin; Florian Gstrein; James M. Blackwell; Marie Krysak; Manish Chandhok; Paul A Nyhus; Charles H. Wallace; Curtis W. Ward; Swaminathan Sivakumar; Elliot N. Tan
- Web page: https://patentgrep.com/patent/US12218052B2

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10W 20/43: Layouts of interconnections
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

## Claims

### Claim 1

A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
subsequent to forming the second set of spacers, removing the plurality of backbone features;
subsequent to removing the plurality of backbone features, forming a third set of spacers along sidewalls of each of the first set of spacers, the third set of spacers having the second material composition;
forming a final feature in each opening between adjacent pairs of spacers of the third set of spacers;
planarizing the first set of spacers, the second set of spacers, the third set of spacers, and the final features to form a target foundation layer; and
using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the plurality of backbone features comprises using a standard lithography operation.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the plurality of backbone features comprises forming a plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide and silicon carbide.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the first set of spacers comprises:
depositing a material of the first set of spacers conformal with the plurality of backbone features using an atomic layer deposition (ALD) process; and
anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of plurality of backbone features.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the first set of spacers comprises selectively growing a material of the first set of spacers along the sidewalls of each of plurality of backbone features.

### Claim 6 (depends on 1)

The method of claim 1, wherein each final feature has a lateral width greater than a lateral width of each spacer from the first set of spacers, the second set of spacers, and the third set of spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein each final feature is formed by a merging of material growth formed along adjacent pairs of spacers of the third set of spacers.

### Claim 8 (depends on 1)

The method of claim 1, wherein each final feature comprises a third material composition.

### Claim 9 (depends on 1)

The method of claim 1, wherein using the target foundation layer to form the metallization layer of the semiconductor structure comprises:
removing all portions of the first material composition to form a first plurality of trenches; and
forming a first plurality of conductive lines in the first plurality of trenches.

### Claim 10 (depends on 9)

The method of claim 9, wherein using the target foundation layer to form the metallization layer of the semiconductor structure further comprises:
forming a second plurality of trenches; and
forming a second plurality of conductive lines in the second plurality of trenches.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first plurality of conductive lines and the second plurality of conductive lines are of a same composition.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first plurality of conductive lines and the second plurality of conductive lines are of a different composition.

### Claim 13 (depends on 1)

The method of claim 1, further comprising forming additional sets of spacers between forming the second set of spacers and the third set of spacers, and prior to removing the plurality of backbone features.

### Claim 14

A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
forming a third set of spacers along sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different than the first material composition, different than the second material composition, and different than the material composition of the plurality of backbone features;
forming a fourth set of spacers along sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition;
forming a fifth set of spacers laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition;
subsequent to forming the fifth set of spacers, removing the plurality of backbone features;
subsequent to removing the plurality of backbone features, forming a sixth set of spacers along sidewalls of each of the first set of spacers and along sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material composition;
forming a final feature in each opening between adjacent pairs of spacers of the sixth set of spacers;
planarizing the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target foundation layer; and
using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the plurality of backbone features comprises using a standard lithography operation.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the plurality of backbone features comprises forming a plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide and silicon carbide.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the first set of spacers comprises:
depositing a material of the first set of spacers conformal with the plurality of backbone features using an atomic layer deposition (ALD) process; and
anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of plurality of backbone features.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the first set of spacers comprises selectively growing a material of the first set of spacers along the sidewalls of each of plurality of backbone features.

### Claim 19 (depends on 14)

The method of claim 14, wherein each final feature has a lateral width greater than a lateral width of each spacers from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, and the sixth set of spacers.

### Claim 20 (depends on 14)

The method of claim 14, wherein each final feature is formed by a merging of material growth formed along adjacent pairs of spacers of the sixth set of spacers.