# US 12,218,051 B2 · Method of manufacturing a semiconductor device including a plurality of circuit components and array of conductive contacts > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,051 B2 - Document ID: US12218051B2 - Status: Granted - Kind: B2 - Application number: 17/869,196 - Filed: 2022-07-20 - Published: 2022-11-10 - Granted: 2025-02-04 - Earliest claimed: 2017-11-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Cheng-Yuan Li; Kuo-Cheng Lee; Yun-Wei Cheng; Yen-Liang Lin - Web page: https://patentgrep.com/patent/US12218051B2 ## CPC - H10W 20/43: Layouts of interconnections - H10W 20/42: Vias, e.g. via plugs - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 72/90: Bond pads, in general - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/00: Package configurations - H10W 46/301: {for alignment} - H10W 46/501: {for use before dicing} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/0198: {batch processes} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/334: {Thermocompression bonding} - H10W 80/335: {Ultrasonic bonding} - H10W 90/732: {between stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, the method comprising: forming a plurality of integrated circuit components over a first wafer, the plurality of integrated circuit components comprising: a first integrated circuit component surrounded by a first seal ring; a second integrated circuit component surrounded by a second seal ring adjacent to the first integrated circuit component; and a scribe region between the first integrated circuit component and the second integrated circuit component; a first array of conductive contacts along a first side of the first integrated circuit component, the first array comprising a first set of rows and a first set of columns, the first array having a first longitudinal axis extending in a first direction; a second array of conductive contacts along a second side of the first integrated circuit component, the second array comprising a second set of rows and a second set of columns, the second array having a second longitudinal axis extending in a second direction perpendicular to the first direction; a third array of conductive contacts along a third side of the first integrated circuit component opposite the first side, the third array of conductive contacts having a third longitudinal axis extending in the first direction; a fourth array of conductive contacts along a fourth side of the first integrated circuit component opposite the second side, the fourth array of conductive contacts having a fourth longitudinal axis extending in the second direction, wherein each of the conductive contacts are located within one of the first array, the second array, the third array, and the fourth array, and wherein each of the first array and the third array extend no farther than one-half of the length of the first integrated circuit component in the first direction and wherein each of the second array and the fourth array extend no farther than one-half of the width of the first integrated circuit component in the second direction; bonding the first array, the second array, the third array, and the fourth array to a second wafer; and dicing the first integrated circuit component from the second integrated circuit component along the scribe region. ### Claim 2 (depends on 1) The method of claim 1, wherein the first array, the second array, the third array, and the fourth array form a first pattern, wherein the second integrated circuit component has a fifth array, a sixth array, a seventh array, and an eighth array, and wherein the fifth array, the sixth array, the seventh array, and the eighth array have the first pattern. ### Claim 3 (depends on 2) The method of claim 2, wherein the first array is aligned with the fifth array. ### Claim 4 (depends on 1) The method of claim 1, wherein the conductive connectors comprise aluminum. ### Claim 5 (depends on 1) The method of claim 1, wherein the conductive connectors comprise copper. ### Claim 6 (depends on 1) The method of claim 1, wherein the conductive connectors comprise a silicide. ### Claim 7 (depends on 6) The method of claim 6, wherein the conductive connectors comprise a nickel silicide. ### Claim 8 A method of manufacturing a semiconductor device, the method comprising: forming a first integrated circuit component over a first wafer, the first integrated circuit component having a top surface, the top surface comprising a plurality of arrays of conductive connectors, wherein each conductive connector within the top surface is located within a first array, a second array, a third array, or a fourth array, wherein each of the first array, the second array, the third array, and the fourth array are located along a perimeter of the first integrated circuit component and wherein each of the first array, the second array, the third array, and the fourth array extend in directions perpendicular to adjacent arrays on the first integrated circuit component; forming a second integrated circuit component over the first wafer and separated from the first integrated circuit component by a scribe region, the second integrated circuit component having a second top surface, the second top surface comprising a second plurality of arrays of conductive connectors, wherein each conductive connector within the second top surface is located within a fifth array, a sixth array, a seventh array, or an eighth array, wherein each of the fifth array, the sixth array, the seventh array, and the eighth array are located along a perimeter of the second integrated circuit component and wherein each of the fifth array, the sixth array, the seventh array, and the eighth array extend in directions perpendicular to adjacent arrays on the second integrated circuit component; bonding the first integrated circuit component and the second integrated circuit component to connectors on a second wafer, the bonding utilizing a bonding wave to expel gases along a path between the first array, the second array, the third array, and the fourth array; and dicing the first integrated circuit component and the second integrated circuit component. ### Claim 9 (depends on 8) The method of claim 8, wherein both the first array and the third array have a length that is less than one-half of a length of the first integrated circuit component. ### Claim 10 (depends on 9) The method of claim 9, wherein both the second array and the fourth array have a width that is less than one-half of a width of the first integrated circuit component. ### Claim 11 (depends on 9) The method of claim 9, wherein the first array and the third array are offset from each other. ### Claim 12 (depends on 11) The method of claim 11, wherein the second array and the fourth array are offset from each other. ### Claim 13 (depends on 8) The method of claim 8, wherein the fifth array is aligned with the first array. ### Claim 14 (depends on 13) The method of claim 13, wherein the sixth array is aligned with the second array. ### Claim 15 A method of manufacturing a semiconductor device, the method comprising: receiving a first wafer, the first wafer comprising a plurality of integrated circuit components separated by scribe regions, wherein each one of the plurality of integrated circuit components has a same pattern of conductive connectors, wherein a first integrated circuit component within the plurality of integrated circuit components comprises: a first array of conductive connectors extending in a first direction; a second array of conductive connectors extending in a second direction perpendicular to the first direction; a third array of conductive connectors extending in the first direction and located on an opposite side of the first integrated circuit component from the first array; and a fourth array of conductive connectors extending in the second direction and located on an opposite side of the first integrated circuit component from the second array; bonding the first array of conductive connectors to a fifth array of conductive connectors on a second wafer; and scribing the first integrated circuit component from a remainder of the first wafer to form a singulated semiconductor device. ### Claim 16 (depends on 15) The method of claim 15, wherein the first array has a length that is less than one-half of a length of the first integrated circuit component. ### Claim 17 (depends on 16) The method of claim 16, wherein the second array has a width that is less than one-half of a width of the first integrated circuit component. ### Claim 18 (depends on 15) The method of claim 15, wherein the first array is offset from the third array. ### Claim 19 (depends on 15) The method of claim 15, wherein the second array is offset from the fourth array. ### Claim 20 (depends on 15) The method of claim 15, wherein the bonding the first array of conductive connectors expels gases from between the arrays.