# US 12,218,049 B2 · Semiconductor structure and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,049 B2 - Document ID: US12218049B2 - Status: Granted - Kind: B2 - Application number: 18/365,210 - Filed: 2023-08-03 - Published: 2023-12-21 - Granted: 2025-02-04 - Earliest claimed: 2020-11-24 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Jen-Yuan Chang; Chia-Ping Lai - Web page: https://patentgrep.com/patent/US12218049B2 ## CPC - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H10D 1/20: Inductors - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/427: {Power or ground buses} - H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive} - H10W 20/494: {changeable by the use of an external beam, e.g. laser beam or ion beam} - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 72/073: {of die-attach connectors} - H10W 76/60: Seals - H10W 90/00: Package configurations - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 72/321: {Structures or relative sizes of die-attach connectors} - H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/792: {between multiple chips} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes: a first die including: a fuse structure including a pair of conductive segments, wherein the pair of conductive segments are separated by a void and one of the pair of conductive segments is electrically connected to a bonding pad of the first die; and a second die over and bonded to the first die, the second die including an inductor electrically connected to the one of the pair of conductive segments. ## Claims ### Claim 1 A semiconductor structure comprising: a first die comprising a fuse structure including a pair of conductive segments, wherein the pair of conductive segments are separated by a void and one of the pair of conductive segments is electrically connected to a bonding pad of the first die, wherein the bonding pad is electrically connected to ground; and a second die over and bonded to the first die, the second die including an inductor electrically connected to the one of the pair of conductive segments. ### Claim 2 (depends on 1) The semiconductor structure according to claim 1, wherein the second die further comprises a through silicon via, and the inductor is electrically connected to the one of the pair of conductive segments through the through silicon via. ### Claim 3 (depends on 2) The semiconductor structure according to claim 2, further comprising: a third die over the second die; a first dielectric layer laterally surrounding the second die; and a through dielectric via extending through the first dielectric layer to electrically connect the third die to the first die. ### Claim 4 (depends on 1) The semiconductor structure according to claim 1, further comprising a third die over and bonded to the second die. ### Claim 5 (depends on 4) The semiconductor structure according to claim 4, wherein the third die comprises a second fuse structure connected to the inductor. ### Claim 6 (depends on 1) The semiconductor structure according to claim 1, wherein the other of the pair of conductive segments is electrically coupled to the inductor. ### Claim 7 (depends on 1) The semiconductor structure according to claim 1, wherein the first die further includes a first substrate, and the fuse structure is disposed over the first substrate. ### Claim 8 (depends on 1) The semiconductor structure according to claim 1, wherein the second die further includes a second substrate, and the inductor is disposed over the second substrate. ### Claim 9 (depends on 8) The semiconductor structure according to claim 8, wherein the second die further includes a through via disposed in the second substrate, electrically connect the inductor to the fuse structure. ### Claim 10 (depends on 1) The semiconductor structure according to claim 1, wherein the fuse structure is surrounded by a second dielectric layer and the void is formed in the second dielectric layer. ### Claim 11 (depends on 10) The semiconductor structure according to claim 10, wherein a density of a first portion of the second dielectric layer closer to the void is greater than a density of a second portion of the second dielectric layer closer to one of the pair of conductive segments. ### Claim 12 (depends on 1) The semiconductor structure according to claim 1, further comprising a fuse control circuit configured to generate a current to blow the fuse structure. ### Claim 13 A semiconductor structure comprising: a first integrated circuit component comprising a fuse structure, the fuse structure being in a blown state; a second integrated circuit component bonded to the first integrated circuit component, the second integrated circuit component comprising an inductor electrically connected to the fuse structure; and a third integrated circuit component bonded to the second integrated circuit component and electrically connected to the first integrated circuit component, wherein the first integrated circuit component further comprises a bonding layer electrically bonding the first integrated circuit component to the second integrated circuit component, wherein the fuse structure is arranged within the bonding layer. ### Claim 14 (depends on 13) The semiconductor structure according to claim 13, wherein the fuse structure comprises a first conductive segment, a second conductive segment and a void between the first and second conductive segments. ### Claim 15 (depends on 13) The semiconductor structure according to claim 13, wherein the first integrated circuit component further comprises a substrate and an interconnection structure over the substrate, wherein the bonding layer is arranged over the interconnection structure. ### Claim 16 (depends on 15) The semiconductor structure according to claim 15, wherein the second integrated circuit component further comprises a through via extending through an entire thickness of the second integrated circuit component, wherein the fuse structure is electrically connected to the inductor through the bonding layer and the through via. ### Claim 17 A semiconductor structure comprising: a first integrated circuit component comprising a first fuse structure; a second integrated circuit component arranged over the first integrated circuit component and comprising an inductor; and a third integrated circuit component arranged over and bonded to the second integrated circuit component, the third integrated circuit component comprising a second fuse structure, wherein the first integrated circuit component comprises a seal ring, and the first fuse structure is electrically connected to ground through the seal ring. ### Claim 18 (depends on 17) The semiconductor structure according to claim 17, wherein the inductor is configured to be electrically connected to at least one of the first and second fuse structures. ### Claim 19 (depends on 17) The semiconductor structure according to claim 17, wherein at least one of the first and second fuse structures is in a blown state. ### Claim 20 (depends on 17) The semiconductor structure according to claim 17, wherein the seal ring is arranged close to a periphery of the first integrated circuit component.