# US 12,218,044 B2 · Semiconductor device

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- Number: US 12,218,044 B2
- Document ID: US12218044B2
- Status: Granted
- Kind: B2
- Application number: 17/722,823
- Filed: 2022-04-18
- Published: 2022-12-22
- Granted: 2025-02-04
- Earliest claimed: 2021-06-16
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Nobuhiro Kinoshita; Shuuichi Kariyazaki; Keita Tsuchiya
- Web page: https://patentgrep.com/patent/US12218044B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 44/209: {Vertical interconnections, e.g. vias}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/072: {of bump connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/30: Die-attach connectors
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/12: characterised by their shape
- H10W 76/63: characterised by their shape or disposition, e.g. between cap and walls of a container
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. The first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. The second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip having a first surface on which a protruding electrode is disposed; and
a wiring substrate having a second surface facing the first surface of the semiconductor chip,
wherein the wiring substrate includes:
a first insulating layer;
a first metal pattern formed on the first insulating layer;
a second insulating layer contacted with the first metal pattern, and formed on the first insulating layer so as to cover the first metal pattern;
a second metal pattern having a first portion facing the protruding electrode and a second portion located around the first portion, and formed on the second insulating layer;
an organic insulating film contacted with the second portion of the second metal pattern, and formed on the second insulating layer so as to expose the first portion of the second metal pattern;
a third insulating layer; and
a third metal pattern formed on the third insulating and to which a reference potential is to be supplied,
wherein the first metal pattern has:
a first lower surface contacted with the first insulating layer; and
a first upper surface opposite the first lower surface, and contacted with the second insulating layer,
wherein the second metal pattern has:
a second lower surface contacted with the second insulating layer; and
a second upper surface contacted with the organic insulating film at the second portion,
wherein the third metal pattern has:
a third lower surface contacted with the third insulating layer; and
a third upper surface opposite the third lower surface, and contacted with the first insulating layer,
wherein a surface roughness of the second upper surface of the second metal pattern is larger than a surface roughness of each of the second lower surface of the second metal pattern and the first upper surface of the first metal pattern, and
wherein a surface roughness of the third upper surface of the third metal pattern is larger than the surface roughness of each of the second lower surface of the second metal pattern and the first upper surface of the first metal pattern.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the protruding electrode is electrically connected with the first metal pattern,
wherein the first metal pattern is electrically connected the second metal pattern by way of a via wiring formed so as to penetrating through the second insulating layer, and
wherein the first metal pattern includes:
a via land portion to which the via wiring is connected; and
a wiring portion formed integrally with the via land portion, and extended in a first direction.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein the second metal pattern is located in a first region with which the semiconductor chip is overlapped, and
wherein, in plan view, the wiring portion of the first metal pattern is extended from the first region toward a second region located around the first region.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein the first metal pattern and the second metal pattern are included in a signal transmission path.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein a length of the wiring portion is longer than a length of each of the second metal pattern, the via wiring and the via land portion, and
wherein an electrical signal flowing the signal transmission path is a high-frequency signal of 30 GHz or more.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein the surface roughness of the second upper surface of the second metal pattern is larger than each of the surface roughness of the second lower surface of the second metal pattern, the surface roughness of the first upper surface of the first metal pattern and a surface roughness of the first lower surface of the first metal pattern, and
wherein the surface roughness of the third upper surface of the third metal pattern is larger than each of the surface roughness of the second lower surface of the second metal pattern, the surface roughness of the first upper surface of the first metal pattern, and a surface roughness of the first lower surface of the first metal pattern.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein a thermal expansion coefficient of the organic insulating film is larger than a thermal expansion coefficient of the second insulating layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein a linear expansion coefficient of the organic insulating film is larger than a linear expansion coefficient of the second insulating layer.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1,
wherein the third insulating layer has a glass fiber therein, but each of the organic insulating film, the first insulating layer and the second insulating layer has no glass fiber therein.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness of the organic insulating film is thinner than a thickness of the second insulating layer.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the surface roughness of the first upper surface of the first metal pattern is smaller than the surface roughness of the first lower surface of the first metal pattern.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1,
wherein a metal film is formed on the first portion of the second metal pattern, and
wherein the protruding electrode and the metal film are electrically connected with each other by way of a solder.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1,
wherein the second metal pattern has a side surface connected to the second upper surface, and contacted with the organic insulating film, and
wherein a surface roughness of the side surface of the second metal pattern is larger than the surface roughness of each of the second lower surface of the second metal pattern, the first upper surface of the first metal pattern and the first lower surface of the first metal pattern.