# US 12,218,043 B2 · Interposer, semiconductor package including the same, and method of fabricating the interposer

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- Number: US 12,218,043 B2
- Document ID: US12218043B2
- Status: Granted
- Kind: B2
- Application number: 17/971,321
- Filed: 2022-10-21
- Published: 2023-02-16
- Granted: 2025-02-04
- Earliest claimed: 2019-12-06
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yukyung Park; Ungcheon Kim; Sungwoo Park; Seungkwan Ryu
- Web page: https://patentgrep.com/patent/US12218043B2

## CPC

- H10W 70/635: {Through-vias}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 72/0198: {batch processes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

## Claims

### Claim 1

An interposer for a semiconductor package, the interposer comprising:
an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface;
a first through-electrode structure and a second through-electrode structure, each passing through the interposer substrate and protruding from the first main surface;
a first passivation layer surrounding a side surface of a protruding portion of the first through-electrode structure and a side surface of a protruding portion of the second through-electrode structure on the first main surface of the interposer substrate, the first passivation layer includes a first material;
a second passivation layer on the first passivation layer between the first through-electrode structure and the second through-electrode structure, the second passivation layer includes a second material that is different from the first material;
a connection terminal structure on the first main surface of the interposer substrate, the connection terminal structure contacts a portion of the first passivation layer, a portion of the second passivation layer, an upper surface of the protruding portion of the first through-electrode structure, and an upper surface of the protruding portion of the second through-electrode structure;
connection pads on the second main surface of the interposer substrate, wherein the connection pads contact lower surfaces of the first through-electrode structure and the second through-electrode structure; and
a redistribution layer on the connection pads and the second main surface of the interposer substrate.

### Claim 2 (depends on 1)

The interposer of claim 1, wherein the upper surface of the protruding portion of the first through-electrode structure, the upper surface of the protruding portion of the second through-electrode structure, an uppermost surface of the first passivation layer, and an upper surface of the second passivation layer are coplanar.

### Claim 3 (depends on 2)

The interposer of claim 2,
wherein a lower surface of the connection terminal structure contacts the upper surface of the protruding portion of the first through-electrode structure, the upper surface of the protruding portion of the second through-electrode structure, at least a portion of the uppermost surface of the first passivation layer, and a portion of the upper surface of the second passivation layer.

### Claim 4 (depends on 2)

The interposer of claim 2,
wherein the lower surface of the connection terminal structure that contacts the second passivation layer is substantially coplanar with the upper surface of the second passivation layer.

### Claim 5 (depends on 1)

The interposer of claim 1,
wherein the redistribution layer includes horizontal wires, contact plugs electrically connecting the horizontal wires to the connection pads, and an interlayer insulating film surrounding each horizontal wire of the horizontal wires and each contact plug of the contact plugs.

### Claim 6 (depends on 1)

The interposer of claim 1,
wherein the connection terminal structure comprises a seed metal layer contacting both the first through-electrode structure and the second through-electrode structure, a first conductor layer provided on the seed metal layer, and a solder metal layer provided on the first conductor layer.

### Claim 7 (depends on 1)

The interposer of claim 1, further comprising:
an alignment key arranged adjacent to the first through-electrode structure.

### Claim 8 (depends on 7)

The interposer of claim 7,
wherein the alignment key passes through the second passivation layer and at least partially passes through the first passivation layer.

### Claim 9 (depends on 8)

The interposer of claim 8,
wherein the second passivation layer has a thickness that decreases in a direction toward the alignment key between the alignment key and the first through-electrode structure arranged adjacent to the alignment key.

### Claim 10 (depends on 8)

The interposer of claim 8,
wherein the first material is a silicon oxide, a silicon nitride, or a silicon oxynitride, and the second material is a photosensitive polymer.

### Claim 11

A semiconductor package comprising:
a package substrate having a recess portion;
an interposer in the recess portion;
on the package substrate; and
a first semiconductor device and a second semiconductor device that are arranged to at least partially overlap the interposer,
wherein the interposer comprises:
an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface;
a first through-electrode structure and a second through-electrode structure, each passing through the interposer substrate and protruding from the first main surface;
a first passivation layer on the first main surface of the interposer substrate, the first passivation layer includes a first material;
a second passivation layer on the first passivation layer between the first through-electrode structure and the second through-electrode structure, the second passivation layer includes a second material that is different from the first material; and
a connection terminal structure on the first main surface of the interposer substrate, and wherein the connection terminal structure contacts the first passivation layer, the second passivation layer, the first through-electrode structure, and the second through-electrode structure.

### Claim 12 (depends on 11)

The semiconductor package of claim 11,
wherein a top surface of the package substrate is substantially coplanar with a top surface of the interposer.

### Claim 13 (depends on 11)

The semiconductor package of claim 11,
wherein the second semiconductor device comprises a memory device including a plurality of stacked memory chips.

### Claim 14 (depends on 11)

The semiconductor package of claim 11,
wherein the interposer partially overlaps each of the first semiconductor device and the second semiconductor device.

### Claim 15 (depends on 11)

The semiconductor package of claim 11,
wherein the connection terminal structure contacts a protruding portion of the first through-electrode structure and a protruding portion of the second through-electrode structure.

### Claim 16

A semiconductor package comprising:
a package substrate having a recess portion;
an interposer disposed on the package substrate and having a first surface and a second surface opposite to the first surface;
a first semiconductor device on the first surface of the interposer, the first semiconductor device is accommodated in the recess portion; and
a second semiconductor device on the second surface of the interposer,
wherein the interposer comprises:
an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface;
a first through-electrode structure and a second through-electrode structure, each passing through the interposer substrate and protruding from the first main surface;
a first passivation layer on the first main surface of the interposer substrate, the first passivation layer includes a first material;
a second passivation layer on the first passivation layer between the first through-electrode structure and the second through-electrode structure, the second passivation layer includes a second material that is different from the first material; and
a connection terminal structure on the first main surface of the interposer substrate, and wherein the connection terminal structure electrically connects the interposer to each of the first semiconductor device and the package substrate.

### Claim 17 (depends on 16)

The semiconductor package of claim 16,
wherein a lower surface of the connection terminal structure contacts an upper surface of a protruding portion of the first through-electrode structure, and an upper surface of a protruding portion of the second through-electrode structure.

### Claim 18 (depends on 16)

The semiconductor package of claim 16,
wherein the interposer further comprises a redistribution layer on the second main surface of the interposer substrate,
wherein the redistribution layer includes horizontal wires, contact plugs electrically connecting the horizontal wires to connection pads, and an interlayer insulating film surrounding each horizontal wire of the horizontal wires and each contact plug of the contact plugs, and
wherein the redistribution layer is disposed between the interposer substrate and the second semiconductor device.

### Claim 19 (depends on 16)

The semiconductor package of claim 16,
wherein the package substrate comprises a base board layer, a top connection pad provided on a top surface of the base board layer, and a bottom connection pad provided on a bottom surface of the base board layer.

### Claim 20 (depends on 16)

The semiconductor package of claim 16,
wherein the interposer entirely overlaps the first semiconductor device and the second semiconductor device.