# US 12,218,040 B2 · Nested interposer with through-silicon via bridge die

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,040 B2
- Document ID: US12218040B2
- Status: Granted
- Kind: B2
- Application number: 17/186,289
- Filed: 2021-02-26
- Published: 2022-09-01
- Granted: 2025-02-04
- Earliest claimed: 2021-02-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Srinivas V. Pietambaram; Debendra Mallik; Kristof Darmawikarta; Ravindranath V. Mahajan; Rahul N. Manepalli
- Web page: https://patentgrep.com/patent/US12218040B2

## CPC

- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/685: comprising multiple insulating layers
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/69: Insulating materials thereof
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/635: {Through-vias}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

## Claims

### Claim 1

An electronic package, comprising:
an interposer, wherein the interposer comprises:
an interposer substrate;
a cavity that passes into but not through the interposer substrate;
a through interposer via (TIV) within the interposer substrate;
an interposer pad electrically coupled to the TIV; and
a first backside pad coupled to the TIV;
a nested component in the cavity, wherein the nested component comprises a component pad coupled to a through-component via;
a core via beneath the nested component, the core via extending from the nested component through the interposer substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad; and
a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

### Claim 2 (depends on 1)

The electronic package of claim 1, wherein the first interconnect and the second interconnect each comprise:
an intermediate pad; and
a bump over the intermediate pad.

### Claim 3 (depends on 2)

The electronic package of claim 2, further comprising:
a dielectric layer over and around the interposer and the nested component.

### Claim 4 (depends on 3)

The electronic package of claim 3, wherein the intermediate pads are over a surface of the dielectric layer.

### Claim 5 (depends on 4)

The electronic package of claim 4, wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the component pad by a second via that passes through a portion of the dielectric layer.

### Claim 6 (depends on 4)

The electronic package of claim 4, wherein the intermediate pad of the first interconnect is directly connected to the interposer pad, and wherein the intermediate pad of the second interconnect is directly connected to the component pad.

### Claim 7 (depends on 1)

The electronic package of claim 1, wherein a centerline of the first interconnect is offset from a centerline of the interposer pad, and wherein a centerline of the second interconnect is offset from a centerline of the component pad.

### Claim 8 (depends on 1)

The electronic package of claim 1, wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

### Claim 9 (depends on 1)

The electronic package of claim 1, wherein the nested component is an active component.

### Claim 10 (depends on 1)

The electronic package of claim 1, further comprising:
a second die, wherein the second die is coupled to the nested component by a third interconnect comprising:
an intermediate pad; and
a bump over the intermediate pad.

### Claim 11 (depends on 10)

The electronic package of claim 10, wherein the nested component electrically couples the first die to the second die.

### Claim 12 (depends on 1)

The electronic package of claim 1, wherein an active surface of the nested component faces towards the die.

### Claim 13 (depends on 1)

The electronic package of claim 1, wherein the interposer substrate comprises glass, ceramic, silicon, silicon carbide, alumina, or organic materials.

### Claim 14

An electronic system, comprising:
a board;
an interposer electrically coupled to the board, wherein the interposer comprises a cavity that passes into but not through an interposer substrate, a nested component in the cavity, a through interposer via (TIV) within the interposer substrate and coupled to a first backside pad, and a core via beneath the nested component, the core via extending from the nested component through the interposer substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad;
a first die electrically coupled to the interposer and the nested component by a first plurality of interconnects; and
a second die electrically coupled to the interposer and the nested component by a second plurality of interconnects.

### Claim 15 (depends on 14)

The electronic system of claim 14, wherein the nested component electrically couples the first die to the second die.

### Claim 16 (depends on 14)

The electronic system of claim 14, further comprising:
a package substrate, wherein the package substrate is electrically coupled to the board, and wherein the interposer is electrically coupled to the package substrate.

### Claim 17

An electronic package, comprising:
an interposer, wherein the interposer comprises:
a glass substrate;
a cavity that passes into but not through the glass substrate;
a through glass via (TGV) within the glass substrate;
an interposer pad electrically coupled to the TGV; and
a first backside pad coupled to the TIV;
a silicon bridge die in the cavity, wherein the silicon bridge die comprises a silicon bridge die pad coupled to a through-silicon via;
a core via beneath the silicon bridge die, the core via extending from the silicon bridge die through the glass substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad; and
a die coupled to the interposer pad by a first interconnect and coupled to the silicon bridge die pad by a second interconnect.

### Claim 18 (depends on 17)

The electronic package of claim 17, wherein the first interconnect and the second interconnect each comprise:
an intermediate pad; and
a bump over the intermediate pad.

### Claim 19 (depends on 18)

The electronic package of claim 18, further comprising:
a dielectric layer over and around the interposer and the silicon bridge die.

### Claim 20 (depends on 19)

The electronic package of claim 19, wherein the intermediate pads are over a surface of the dielectric layer.

### Claim 21 (depends on 20)

The electronic package of claim 20, wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the silicon bridge die pad by a second via that passes through a portion of the dielectric layer.

### Claim 22 (depends on 20)

The electronic package of claim 20, wherein the intermediate pad of the first interconnect is directly connected to the interposer pad, and wherein the intermediate pad of the second interconnect is directly connected to the silicon bridge die pad.

### Claim 23 (depends on 17)

The electronic package of claim 17, wherein a centerline of the first interconnect is offset from a centerline of the interposer pad, and wherein a centerline of the second interconnect is offset from a centerline of the silicon bridge die pad.

### Claim 24 (depends on 17)

The electronic package of claim 17, wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

### Claim 25 (depends on 17)

The electronic package of claim 17, further comprising:
a second die, wherein the second die is coupled to the silicon bridge die by a third interconnect comprising:
an intermediate pad; and
a bump over the intermediate pad.