# US 12,218,039 B2 · Semiconductor package

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- Number: US 12,218,039 B2
- Document ID: US12218039B2
- Status: Granted
- Kind: B2
- Application number: 18/311,621
- Filed: 2023-05-03
- Published: 2023-08-31
- Granted: 2025-02-04
- Earliest claimed: 2020-09-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jeonggi Jin; Gyuho Kang; Solji Song; Un-Byoung Kang; Ju-Il Choi
- Web page: https://patentgrep.com/patent/US12218039B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/6525: {for securing the interconnections to the substrate, e.g. to prevent peeling}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

## Claims

### Claim 1

A method of a semiconductor package, the method comprising,
forming a redistribution substrate; and
mounting a semiconductor chip on the redistribution substrate,
wherein forming the redistribution substrate comprises:
forming a first redistribution pattern;
forming a recess portion at an upper part of the first redistribution pattern; and
forming a second redistribution pattern on the first redistribution pattern,
wherein the second redistribution pattern includes a via portion and a wire portion on the via portion, the via portion fills the recess portion, and
wherein the recess portion includes an undercut having a downwardly convex bottom surface.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor package according to claim 1, wherein the bottom surface of the via portion is lower than an upper surface of the first redistribution pattern.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor package according to claim 1, further comprising, forming a seed layer along the first redistribution pattern and the recess portion before forming the via portion and the wire portion.

### Claim 4 (depends on 3)

The method of manufacturing a semiconductor package according to claim 3, wherein a thickness of the seed layer contacting the via portion is smaller than the thickness of the seed layer contacting the wire portion.

### Claim 5 (depends on 4)

The method of manufacturing a semiconductor package according to claim 4, wherein thickness of the seed layer on the via portion is 30% to 80% of the thickness of the seed layer on the wire portion.

### Claim 6 (depends on 3)

The method of manufacturing a semiconductor package according to claim 3, wherein the downwardly convex bottom surface of the seed layer is positioned at a level lower than a top surface of the first redistribution pattern.

### Claim 7 (depends on 3)

The method of manufacturing a semiconductor package according to claim 3, wherein the seed layer is positioned between the first redistribution pattern and the second redistribution pattern.

### Claim 8 (depends on 4)

The method of manufacturing a semiconductor package according to claim 4, wherein forming the seed layer is including a deposition process of forming a seed layer on the wire portion to a thickness of 200 Å to 3000 Å.

### Claim 9 (depends on 3)

The method of manufacturing a semiconductor package according to claim 3, wherein forming the second redistribution pattern is forming through an electroplating process using the seed layer as an electrode.

### Claim 10 (depends on 1)

The method of manufacturing a semiconductor package according to claim 1, further comprising, forming a mold layer disposed on the redistribution substrate and covering the semiconductor chip.

### Claim 11

A method of a semiconductor package, the method comprising,
preparing a carrier substrate;
forming a redistribution substrate on the carrier substrate; and
mounting a semiconductor chip on the redistribution substrate,
wherein forming the redistribution substrate comprises:
forming a first redistribution pattern;
forming an insulating layer covering the first redistribution pattern;
patterning the insulating layer to expose a portion of an upper surface of the first redistribution pattern;
etching the exposed upper surface of the first redistribution pattern to form a recess portion; and
forming a second redistribution pattern on the first redistribution pattern,
wherein the second redistribution pattern includes a via portion and a wire portion on the via portion; and
wherein a bottom surface of the via portion is at a level lower than the upper surface of the first redistribution pattern covered by the insulating layer.

### Claim 12 (depends on 11)

The method of manufacturing a semiconductor package according to claim 11, further comprising, removing the carrier substrate.

### Claim 13 (depends on 12)

The method of manufacturing a semiconductor package according to claim 12, further comprising, forming a solder pattern on the redistribution substrate.

### Claim 14 (depends on 11)

The method of manufacturing a semiconductor package according to claim 11, wherein mounting the semiconductor chip includes forming bonding bumps between the redistribution substrate and the semiconductor chip.

### Claim 15 (depends on 1)

The method of manufacturing a semiconductor package according to claim 1, wherein forming the recess portion includes etching an exposed upper surface of the first redistribution pattern to form the recess portion.