# US 12,218,036 B2 · Package substrate having integrated passive device(s) between leads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,036 B2 - Document ID: US12218036B2 - Status: Granted - Kind: B2 - Application number: 18/177,273 - Filed: 2023-03-02 - Published: 2023-06-29 - Granted: 2025-02-04 - Earliest claimed: 2020-04-17 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Rajen Manicon Murugan; Yiqi Tang - Web page: https://patentgrep.com/patent/US12218036B2 ## CPC - H10W 70/451: {Multilayered leadframes} - H10W 70/685: comprising multiple insulating layers - H10W 70/04: of leadframes - H10W 70/435: {of insulating layers on leadframes, e.g. bridging members} - H10W 70/475: {Capacitors in combination with leadframes} - H10W 70/635: {Through-vias} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/014: {using batch processing} - H10W 74/016: {using moulds} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/072: {of bump connectors} - H10W 72/07236: {Soldering or alloying} - H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07254: {changes in dispositions} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/225: {Bumps having a filler embedded in a matrix} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device. ## Claims ### Claim 1 A method, comprising: forming a multilayer package substrate, comprising: forming a top layer including top filled vias through a top dielectric layer and a top metal layer providing a top surface of a plurality of leads and a plurality of traces connected to the plurality of leads, and forming a bottom layer including bottom filled vias including contact pads through a bottom dielectric layer and a bottom metal layer, wherein the top filled vias are for connecting the bottom metal layer to the top metal layer, and wherein the bottom filled vias are for connecting the bottom metal layer to the contact pads; attaching an integrated circuit (IC) die having a semiconductor surface including circuitry, with nodes in the circuitry electrically connected to bond pads, wherein the IC die is flipchip mounted onto the plurality of leads to provide an electrical connection to the bond pads; attaching at least one passive device surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the plurality of leads; and forming a mold compound for encapsulating at least the IC die and the at least one passive device. ### Claim 2 (depends on 1) The method of claim 1, wherein the IC die comprises pillars on the bond pads, and wherein solder is on the top of the pillars. ### Claim 3 (depends on 1) The method of claim 1, wherein the IC die comprises a power device. ### Claim 4 (depends on 3) The method of claim 3, wherein the power device comprises a power converter, a power amplifier, a power switch, a power regulator, a DC/DC converter, or an AC/DC converter. ### Claim 5 (depends on 1) The method of claim 1, wherein at least a portion of the plurality of leads have a spacing of less than 0.6 mm between neighboring ones of the plurality of leads. ### Claim 6 (depends on 1) The method of claim 1, wherein the passive device comprises an inductor. ### Claim 7 (depends on 1) The method of claim 1, wherein the passive device comprises a first type of passive device and a second type of passive device. ### Claim 8 (depends on 1) The method of claim 1, wherein the multilayer package substrate consists of the top layer and the bottom layer. ### Claim 9 (depends on 1) The method of claim 1, wherein the at least one passive device comprises a first capacitor and a second capacitor, and wherein the first capacitor and the second capacitor are both in a capacitance range from 0.5 pF to 100 μF. ### Claim 10 (depends on 9) The method of claim 9, wherein the first capacitor and second capacitor are connected in parallel. ### Claim 11 A method, comprising: forming a multilayer package substrate, comprising: forming a top layer including top filled vias through a top dielectric layer and a top metal layer providing a top surface of a plurality of leads and a plurality of traces connected to the plurality of leads, and forming a bottom layer including bottom filled vias including contact pads through a bottom dielectric layer and a bottom metal layer, wherein the top filled vias are for connecting the bottom metal layer to the top metal layer, and wherein the bottom filled vias are for connecting the bottom metal layer to the contact pads; attaching an integrated circuit (IC) die having a semiconductor surface including circuitry, with nodes in the circuitry electrically connected to bond pads, wherein the IC die is flipchip mounted onto the plurality of leads to provide an electrical connection to the bond pads; attaching at least one passive device surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the plurality of leads; and forming a mold compound for encapsulating at least the IC die and the at least one passive device, wherein the at least one passive device comprises a first capacitor and a second capacitor, and wherein the forming the multilayer package substrate further comprises providing a bridge portion together with a first and a second of the top filled vias positioned to electrically connect adjacent first and second traces of the plurality of traces to connect the first capacitor and second capacitor in series. ### Claim 12 (depends on 11) The method of claim 11, wherein the first capacitor and the second capacitor are both in a capacitance range from 0.5 pF to 100 μF. ### Claim 13 (depends on 11) The method of claim 11, wherein the IC die comprises pillars on the bond pads, and wherein solder is on the top of the pillars. ### Claim 14 (depends on 11) The method of claim 11, wherein the IC die comprises a power device. ### Claim 15 (depends on 14) The method of claim 14, wherein the power device comprises a power converter, a power amplifier, a power switch, a power regulator, a DC/DC converter, or an AC/DC converter. ### Claim 16 (depends on 11) The method of claim 11, wherein at least a portion of the plurality of leads have a spacing of less than 0.6 mm between neighboring ones of the plurality of leads. ### Claim 17 (depends on 11) The method of claim 11, wherein the multilayer package substrate consists of the top layer and the bottom layer. ### Claim 18 A method, comprising: forming a multilayer package substrate, comprising: forming a top layer comprising a plurality of top metal vias through a top dielectric layer and a top metal layer providing a top surface of a plurality of leads and a plurality of traces connected to the plurality of leads, and forming a bottom layer including a plurality of bottom metal vias including contact pads through a bottom dielectric layer and a bottom metal layer, wherein the plurality of top metal vias connect the bottom metal layer to the top metal layer, and wherein the plurality of bottom metal vias connect the bottom metal layer to the contact pads, and wherein the plurality of top metal vias and the plurality of bottom metal vias are filled; attaching an integrated circuit (IC) die having a semiconductor surface including circuitry, with nodes in the circuitry electrically connected to bond pads, wherein the IC die is flipchip mounted onto the plurality of leads to provide an electrical connection to the bond pads; attaching at least a first capacitor and a second capacitor, the first capacitor and the second capacitor being surface mounted on the top metal layer by an electrically conductive material, electrically connected between at least one adjacent pair of the plurality of leads; forming a bridge comprising at least a first top metal via and a second top metal via of the plurality of top metal vias positioned to electrically connect adjacent first and second traces of the plurality of traces to connect the first capacitor to the second capacitor; and forming a mold compound for encapsulating at least the IC die, the first capacitor and the second capacitor. ### Claim 19 (depends on 18) The method of claim 18, wherein the first capacitor and second capacitor are connected in parallel by the bridge. ### Claim 20 (depends on 18) The method of claim 18, wherein the first capacitor and second capacitor are connected in series by the bridge.