# US 12,218,034 B2 · Semiconductor structure and method for manufacturing semiconductor structure

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- Number: US 12,218,034 B2
- Document ID: US12218034B2
- Status: Granted
- Kind: B2
- Application number: 17/650,659
- Filed: 2022-02-10
- Published: 2022-05-26
- Granted: 2025-02-04
- Earliest claimed: 2020-11-16
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Ping-Heng Wu
- Web page: https://patentgrep.com/patent/US12218034B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/43: Layouts of interconnections
- H10W 70/635: {Through-vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a base, a conductive pillar at least located in the base, connecting structures and an electrical connection layer. At least one connecting structure is electrically connected to an end of the conductive pillar, the material of the connecting structure is different from that of the conductive pillar, and a total area of an orthographic projection of the connecting structure on the base is less than an area of an orthographic projection of the conductive pillar on the base. The electrical connection layer is electrically connected to an end of the connecting structure distal from the conductive pillar.

## Claims

### Claim 1

A semiconductor structure, comprising:
a base;
a conductive pillar at least located in the base;
at least two connecting structures spaced apart, at least one connecting structure being electrically connected to an end of the conductive pillar, a material of the connecting structure being different from that of the conductive pillar, and a total area of an orthographic projection of the connecting structure on the base being less than an area of an orthographic projection of the conductive pillar on the base;
an electrical connection layer electrically connected to an end of the connecting structure distal from the conductive pillar;
at least one first structure, part of first structures being arranged around the connecting structures or interspersed in a spacing of a plurality of connecting structures, and the first structures being configured to generate or transmit an electric signal of the semiconductor structure; and
at least another connected structure is electrically connected with the first structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the connecting structure has a first end surface and an opposite second end surface, the first end surface is in contact with an end surface of the conductive pillar or the first end surface is embedded into the conductive pillar, and the second end surface is in contact with an end surface of the electrical connection layer or the second end surface is embedded into the electrical connection layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of the total area of the orthographic projection of the connecting structure on the substrate to the area of the orthographic projection of the conductive pillar on the substrate is ranged from 1/10 to ⅕.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the conductive pillar is a through silicon via (TSV).

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a thermal expansion coefficient of the material of the connecting structure is less than that of the material of the conductive pillar.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the material of the connecting structure comprises doped polycrystalline silicon and a metal material.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein one connecting structure forms a closed ring structure, and the first structures are located around the connecting structure.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein at least two connecting structures form a ring structure, and the first structures are located in the spacings of the plurality of connecting structures.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein at least two connecting structures are spaced around a central axis of the conductive pillar, and the first structures are located in the spacings of the plurality of connecting structures.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the connecting structure and the first structures are fin-shaped structures, and the first structures are located at two sides of the connecting structure.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the base comprises a substrate and a dielectric layer stacked in sequence, the electrical connection layer is located in the dielectric layer, and the connecting structures are located in the dielectric layer or the connecting structures are located in the dielectric layer or the substrate.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein a thermal expansion coefficient of the material of the connecting structure is less than that of a material of the electrical connection layer.