# US 12,218,029 B2 · Semiconductor device with improved performance in operation and improved flexibility in the arrangement of power chips

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- Number: US 12,218,029 B2
- Document ID: US12218029B2
- Status: Granted
- Kind: B2
- Application number: 17/824,484
- Filed: 2022-05-25
- Published: 2022-12-01
- Granted: 2025-02-04
- Earliest claimed: 2021-05-26
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Edward Fuergut; Anton Mauder; Stephan Voss; Martin Gruber
- Web page: https://patentgrep.com/patent/US12218029B2

## CPC

- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 42/267: {Patterned shielding planes}
- H10W 70/468: {Circuit boards}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/534: {being rectangular}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/631: {Shapes of strap connectors}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/763: {between laterally-adjacent chips}
- H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

## Claims

### Claim 1

A semiconductor device, comprising:
an insulating interposer comprising an insulative layer disposed between a lower metal layer and a first upper metal layer;
at least one semiconductor transistor die attached to the first upper metal layer, the semiconductor transistor die comprising a first lower main face and a second upper main face opposite to the first main face and a drain or collector electrode pad disposed on the first main face and electrically connected to the first upper metal layer of the insulating interposer, a source or emitter electrode pad disposed on the second main face, and a gate electrode pad disposed on the second main face;
a leadframe connected to the insulating interposer, the leadframe comprising a plurality of leads,
wherein a first lead is connected with the first upper metal layer of the insulating interposer, and a second lead is connected with the source electrode pad,
wherein the semiconductor device is characterized by the insulating interposer comprising a second upper metal layer and the leadframe comprising a third lead which is connected with the second upper metal layer, and
wherein an electrical connector is connected between the gate electrode pad and the second upper metal layer so that it extends in a direction which is essentially orthogonal to an extension direction of a first electrical connector.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the second upper metal layer extends laterally besides the first upper metal layer and in a direction towards the leadframe and is connected by a further electrical connector to the third lead of the leadframe.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the insulating interposer comprises one of a direct copper bond (DCB), an active metal braze (AMB) or an insulated metal substrate (IMS).

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor transistor die comprises an IGBT or MOSFET die.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a first semiconductor transistor die and a second semiconductor transistor die both attached to the first metal layer, wherein the first and second semiconductor dies are connected in parallel.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising the semiconductor die comprising a source/sense pad; the insulating interposer comprising a third upper metal layer wherein a further electrical connector is connected between the source/sense pad and the third upper metal layer.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the third upper metal layer is disposed between the first upper metal layer and the second upper metal layer.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the first lead is divided into two parts, wherein a first part is connected with a front end portion and a second part is connected with a back end portion of the first upper metal layer of the insulating interposer.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein an area of the first upper metal layer is smaller than an area of the lower metal layer of the insulating interposer.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, further comprising a further metal layer which at least partially surrounds the first upper metal layer of the insulating interposer, the further metal layer being connected with the second lead or a fourth lead.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the interposer comprises a further upper metal layer which is connected with the source pad of the semiconductor die and with the second lead of the leadframe.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the insulating interposer comprises a strip-like further upper metal layer which extends lateral besides the first upper metal layer and in a direction towards the leadframe and is connected with the second lead.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, further comprising an electrical device connected between one of the metal layers of the insulating interposer, the electrical device being one or more of a suppressor diode, an avalanche diode, or any other device configured to actively turn-off the gate in case of an overvoltage, an overcurrent or a short circuit.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein the lower metal layer of the interposer comprises an area which is reduced for an amount of at least 10% or at least 20% or at least 30% at the front end side of the interposer.