# US 12,218,026 B2 · Package structure for heat dissipation

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- Number: US 12,218,026 B2
- Document ID: US12218026B2
- Status: Granted
- Kind: B2
- Application number: 18/332,957
- Filed: 2023-06-12
- Published: 2023-10-12
- Granted: 2025-02-04
- Earliest claimed: 2016-12-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; Sung-Feng Yeh; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US12218026B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 72/0198: {batch processes}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/635: {Through-vias}
- H10W 70/655: Fan-out layouts
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

## Claims

### Claim 1

A method comprising:
providing a structure comprising:
a carrier wafer, and
a first device wafer with an adhesion layer between the carrier wafer and the first device wafer;
forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer;
forming a first protective layer on the structure before the plurality of first ablation structures are formed; and
removing the first protective layer after the plurality of first ablation structures are formed.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the plurality of first ablation structures has a portion that extends into but not through the carrier wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first device wafer comprises a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first device wafer comprises a first side of the first device wafer and a second side of the first device wafer opposite to the first side of the first device wafer, the first side of the first device wafer being in contact with the adhesion layer, and the second side of the first device wafer comprising a plurality of first bonding contacts configured to be bonded to a second device wafer.

### Claim 5 (depends on 4)

The method of claim 4, forming a plurality of second ablation structures in the second device wafer according to the plurality of first ablation structures, each of the plurality of second ablation structures extending through a portion of the second device wafer, wherein at least a majority of a cross-section of the plurality of second ablation structures overlaps with a cross-section of the plurality of first ablation structures when overlaying a cross-section of the second device wafer having the cross-section of the plurality of second ablation structures.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plurality of first ablation structures comprises molding compound.

### Claim 7

A method comprising:
providing a first structure comprising:
a carrier wafer, and
a first device wafer with an adhesion layer between the carrier wafer and the first device wafer;
forming a plurality of first ablation structures in the first structure, each of the plurality of first ablation structures extending toward the first device wafer; and
attaching a second structure over the first ablation structures.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first device wafer comprises a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
forming a first protective layer on the first structure before the plurality of first ablation structures are formed; and
patterning the first protective layer into a first mask.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second structure comprises a heat spreader.

### Claim 11 (depends on 10)

The method of claim 10, wherein the attaching the second structure comprises applying a thermal interface material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the applying the thermal interface material places the thermal interface material into the first ablation structures.

### Claim 13 (depends on 12)

The method of claim 12, wherein after the forming the plurality of first ablation structures the plurality of first ablation structures comprises sidewalls, the sidewalls comprising a gap-fill material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first mask is in physical contact with the gap-fill material.

### Claim 15 (depends on 14)

The method of claim 14, wherein the thermal interface material is in physical contact with the first mask.

### Claim 16

A method comprising:
providing a structure comprising:
a carrier wafer, and
a first device wafer with an adhesion layer between the carrier wafer and the first device wafer;
stacking a second device wafer to the first device wafer, the second device wafer having a plurality of second dies; and
forming a plurality of first ablation structures in the structure, wherein adjacent second dies are separated by one of the first ablation structures.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming a plurality of second ablation structures in the structure, each of the plurality of second ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the plurality of first ablation structures are formed in the second device wafer according to the plurality of second ablation structures, wherein at least a majority of a cross-section of the plurality of first ablation structures overlaps with a cross-section of the plurality of second ablation structures when overlaying a cross-section of the carrier wafer having the cross-section of the plurality of second ablation structures and a cross-section of the second device wafer having the cross-section of the plurality of first ablation structures.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first device wafer comprises a first side of the first device wafer and a second side of the first device wafer opposite to the first side of the first device wafer, the first side of the first device wafer being in contact with the adhesion layer, and the second side of the first device wafer comprising a plurality of first bonding contacts configured to be bonded to a second device wafer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
providing a plurality of separated bonded semiconductor devices by dicing through at least the carrier wafer, the adhesion layer, the first device wafer and the second device wafer along at least the second ablation structures and the second ablation structures, wherein each of the plurality of separated bonded semiconductor devices comprises a die from each of the first device wafer and the second device wafer.