# US 12,218,024 B2 · Semiconductor device and fabrication method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,024 B2 - Document ID: US12218024B2 - Status: Granted - Kind: B2 - Application number: 18/507,123 - Filed: 2023-11-13 - Published: 2024-03-07 - Granted: 2025-02-04 - Earliest claimed: 2018-11-05 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Motoyoshi Kubouchi; Soichi Yoshida - Web page: https://patentgrep.com/patent/US12218024B2 ## CPC - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) - G01K 13/00: Thermometers specially adapted for specific purposes - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/53: the imperfections being within the semiconductor body - H10D 64/111: {Field plates} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 84/617: {Combinations of vertical BJTs and only diodes} - H10P 32/171: {being group IV material} - H10P 32/18: {Diffusion lifetime killers} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10W 72/926: {Multiple bond pads having different sizes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; a temperature sensing unit provided above the semiconductor substrate; and an upper lifetime control region that is provided within the semiconductor substrate and in a region overlapping with the temperature sensing unit in top view and includes a lifetime killer, wherein the temperature sensing unit does not include the lifetime killer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: an active section including a transistor section and a diode section provided on the semiconductor substrate; and an edge termination structure that is provided in the semiconductor substrate and surrounds the active section in top view. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising: a well region of a second conductivity type provided below the temperature sensing unit. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising: an active section including a transistor section and a diode section provided on the semiconductor substrate, wherein the transistor section and the diode section include a trench portion that extends from a surface of the semiconductor substrate into the semiconductor substrate, and a portion of the trench portion is provided inside the well region. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising: an active section including a transistor section and a diode section provided on the semiconductor substrate, wherein the diode section includes a cathode region of a second conductivity type that is provided inside the semiconductor substrate and is exposed at a lower surface of the semiconductor substrate, and the upper lifetime control region is formed continuously with the temperature sensing unit and the diode section. ### Claim 6 (depends on 3) The semiconductor device according to claim 3, wherein the upper lifetime control region is formed at a deeper position than a lower end of the well region. ### Claim 7 (depends on 3) The semiconductor device according to claim 3, wherein the upper lifetime control region is formed at a same depth position as the well region. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon carbide substrate. ### Claim 10 (depends on 2) The semiconductor device according to claim 2, further comprising: a well region of a second conductivity type provided below the temperature sensing unit. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the transistor section and the diode section include a trench portion that extends from a surface of the semiconductor substrate into the semiconductor substrate, and a portion of the trench portion is provided inside the well region. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein the upper lifetime control region is formed at a deeper position than a lower end of the well region. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein the upper lifetime control region is formed at a same depth position as the well region. ### Claim 14 A fabrication method of a semiconductor device, the method comprising: after introducing a lifetime killer from an upper surface side of a semiconductor substrate and forming an upper lifetime control region within the semiconductor substrate, forming a temperature sensing unit above the semiconductor substrate and at a position overlapping with the upper lifetime control region in top view.