# US 12,218,023 B2 · Semiconductor package and method of forming the same

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- Number: US 12,218,023 B2
- Document ID: US12218023B2
- Status: Granted
- Kind: B2
- Application number: 18/515,264
- Filed: 2023-11-21
- Published: 2024-03-14
- Granted: 2025-02-04
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Sheng Lin; Chin-Hua Wang; Shu-Shen Yeh; Chien-Hung Chen; Po-Yao Lin; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US12218023B2

## CPC

- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10P 72/7416: {used during dicing or grinding}
- H10W 70/611: {for connecting multiple chips together}
- H10W 72/072: {of bump connectors}
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. The underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution structure;
a first semiconductor device disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface, the first sub-surface is connected with the first bottom surface, the second sub-surface is connected with the first top surface, a first obtuse angle is between the first sub-surface and the first bottom surface, and a first acute angle is between the second sub-surface and the first top surface;
a second semiconductor device disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface, the third sub-surface is connected with the second bottom surface, the fourth sub-surface is connected with the second top surface, a second obtuse angle is between the third sub-surface and the second bottom surface, and a second acute angle is between the fourth sub-surface and the second top surface;
an underfill layer between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure; and
an encapsulant encapsulating the first semiconductor device, the second semiconductor device and the underfill layer.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein a first minimum distance between the first bottom surface and the second bottom surface is greater than a second minimum distance between the first top surface and the second top surface.

### Claim 3 (depends on 2)

The semiconductor package according to claim 2, wherein the first minimum distance between the first bottom surface and the second bottom surface is greater than 1.25 times of the second minimum distance between the first top surface and the second top surface.

### Claim 4 (depends on 3)

The semiconductor package according to claim 3, wherein the second minimum distance between the first top surface and the second top surface is less than 400 μm.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, wherein
a first included angle between the first sub-surface and a first virtual plane perpendicular to the first top surface is greater than a second included angle between the second sub-surface and a second virtual plane perpendicular to the first top surface; and
a third included angle between the third sub-surface and a third virtual plane perpendicular to the second top surface is greater than a fourth included angle between the fourth sub-surface and a fourth virtual plane perpendicular to the second top surface.

### Claim 6 (depends on 5)

The semiconductor package according to claim 5, wherein each of the first included angle, the second included angle, the third included angle and the fourth included angle is less than 45 degree and greater than 0 degree.

### Claim 7 (depends on 1)

The semiconductor package according to claim 1, wherein the first sub-surface, the second sub-surface, the third sub-surface and the fourth sub-surface are inclined surfaces.

### Claim 8 (depends on 1)

The semiconductor package according to claim 1, wherein a third obtuse angle is between the first sub-surface and the second sub-surface, and a forth obtuse angle is between the third sub-surface and the fourth sub-surface.

### Claim 9

A semiconductor package, comprising:
a redistribution structure;
a first semiconductor device disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device comprises a first portion and a second portion stacking on the first portion along a first direction, the first portion has a first side surface, the second portion has a second side surface, a slope of the first side surface is different from a slope of the second side surface, a first surface of the first portion connects with the first side surface and is a bottom surface of the first semiconductor device, a second surface of the second portion connects with the second side surface and is a top surface of the first semiconductor device, a first obtuse angle is between first side surface and the first surface, and a first acute angle is between the second side surface and the second surface;
a second semiconductor device disposed aside the first semiconductor device and electrically connected with the redistribution structure, wherein the second semiconductor device comprises a third portion and a fourth portion stacking on the third portion along the first direction, the third portion has a third side surface, the fourth portion has a fourth side surface, a space is between the first semiconductor device and the second semiconductor device and is sandwiched by the first side surface, the second side surface, the third side surface and the fourth side surface, a slope of the third side surface is different from a slope of the fourth side surface, a third surface of the third portion connects with the third side surface and is a bottom surface of the second semiconductor device, a fourth surface of the fourth portion connects with the fourth side surface and is a top surface of the second semiconductor device, a second obtuse angle is between third side surface and the third surface, and a second acute angle is between the fourth side surface and the fourth surface;
an underfill layer filling the space between the first semiconductor device and the second semiconductor device; and
an encapsulant encapsulating the first semiconductor device, the second semiconductor device and the underfill layer.

### Claim 10 (depends on 9)

The semiconductor package according to claim 9, wherein
a first included angle between the first side surface and a first virtual plane parallel with the first direction is greater than a second included angle between the second side surface and a second virtual plane parallel with the first direction; and
a third included angle between the third side surface and a third virtual plane parallel with the first direction is greater than a fourth included angle between the fourth side surface and a fourth virtual plane parallel with the first direction.

### Claim 11 (depends on 10)

The semiconductor package according to claim 10, wherein along the first direction, a thickness of the first portion is equal to or greater than a thickness of the second portion, a thickness of the third portion is equal to or greater than a thickness of the fourth portion, and each of the first included angle, the second included angle, the third included angle and the fourth included angle is less than 30 degree and greater than 0 degree.

### Claim 12 (depends on 10)

The semiconductor package according to claim 10, wherein along the first direction, a thickness of the first portion is less than a thickness of the second portion, a thickness of the third portion is less than a thickness of the fourth portion, and each of the first included angle, the second included angle, the third included angle and the fourth included angle is less than 45 degree and greater than 0 degree.

### Claim 13 (depends on 10)

The semiconductor package according to claim 10, wherein the first included angle is the same as the third included angle, and the second included angle is the same as the fourth included angle.

### Claim 14 (depends on 9)

The semiconductor package according to claim 9, wherein the first inclined side surface is separated from the third inclined side surface by a maximum distance along a second direction perpendicular to the first direction, the second inclined side surface is separated from the fourth inclined side surface by a minimum distance along the second direction, the minimum distance is less than 400 μm, and the maximum distance is greater than 1.25 times of the minimum distance.

### Claim 15 (depends on 9)

The semiconductor package according to claim 9, further comprising
first bonding structures in contact with the first portion of the first semiconductor device; and
second bonding structures in contact with the third portion of the second semiconductor device.

### Claim 16 (depends on 9)

The semiconductor package according to claim 9, further comprising:
electrical terminals disposed on the redistribution structure opposite to the first semiconductor device and the second semiconductor device and electrically connected with the redistribution structure.

### Claim 17 (depends on 9)

The semiconductor package according to claim 9, wherein a third obtuse angle is between the first side surface and the second side surface, and a forth obtuse angle is between the third side surface and the fourth side surface.

### Claim 18

A method of forming a semiconductor package comprising:
providing a first semiconductor device with a first side surface connecting with a first bottom surface and a first top surface, wherein the first side surface comprises a first sub-surface and a second sub-surface, the first sub-surface is connected with the first bottom surface, the second sub-surface is connected with the first top surface, a first obtuse angle is between the first sub-surface and the first bottom surface, and a first acute angle is between the second sub-surface and the first top surface;
providing a second semiconductor device with a second side surface connecting with a second bottom surface and a second top surface, wherein the second side surface comprises a third sub-surface and a fourth sub-surface, the third sub-surface is connected with the second bottom surface, the fourth sub-surface is connected with the second top surface, a second obtuse angle is between the third sub-surface and the second bottom surface, and a second acute angle is between the fourth sub-surface and the second top surface;
forming a redistribution structure;
bonding the first semiconductor device and the second semiconductor device to the redistribution structure to have the first side surface facing toward the second side surface;
forming an underfill layer between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure; and
encapsulating the first semiconductor device, the second semiconductor device and the underfill layer by an encapsulant.

### Claim 19 (depends on 18)

The method of forming the semiconductor package according to claim 18, wherein the first side surface of the first semiconductor device is formed by a first blade cutting process, the second side surface of the second semiconductor device is formed by a second blade cutting process, and the first blade cutting process is the same as the second blade cutting process.

### Claim 20 (depends on 18)

The method of forming the semiconductor package according to claim 18, wherein the first side surface of the first semiconductor device is formed by a first blade cutting process, the second side surface of the second semiconductor device is formed by a second blade cutting process, and the first blade cutting process is different from the second blade cutting process.