# US 12,218,021 B2 · Semiconductor packages and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,021 B2 - Document ID: US12218021B2 - Status: Granted - Kind: B2 - Application number: 18/327,030 - Filed: 2023-05-31 - Published: 2023-09-28 - Granted: 2025-02-04 - Earliest claimed: 2020-07-20 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Jung-Wei Cheng; Jiun-Yi Wu; Hsin-Yu Pan; Tsung-Ding Wang; Yu-Min Liang; Wei-Yu Chen - Web page: https://patentgrep.com/patent/US12218021B2 ## CPC - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/74: {using temporarily an auxiliary support} - H10W 40/613: {for stacked arrangements of a plurality of semiconductor devices} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern. ## Claims ### Claim 1 A semiconductor package, comprising: a circuit board structure, comprising: a core layer and first and second build-up layers respectively located on two surfaces of the core layer; and first conductive patterns located on the first build-up layer; a first redistribution layer structure disposed over the circuit board structure; and first bonding elements disposed on the first conductive patterns and located between and electrically connected to the first redistribution layer structure and the circuit board structure, wherein a portion of an encapsulation layer is disposed between the first redistribution layer structure and the circuit board structure and another portion of the encapsulation layer covers a sidewall of the circuit board structure, and wherein a sidewall of the first redistribution layer structure is flush with a sidewall of the encapsulation layer. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein the first conductive patterns comprise inner conductive patterns and outer conductive patterns around the inner conductive patterns, the first bonding elements comprise inner bonding elements disposed on the inner conductive patterns and outer bonding elements disposed on the outer conductive patterns, and wherein the outer bonding elements completely cover top surfaces and sidewalls of the outer conductive patterns, and the inner bonding elements partially cover top surfaces of the inner conductive patterns. ### Claim 3 (depends on 2) The semiconductor package according to claim 2, wherein a width of the outer conductive patterns is less than a width of the inner conductive patterns. ### Claim 4 (depends on 2) The semiconductor package according to claim 2, wherein tops of the outer bonding elements are flush with tops of the inner bonding elements. ### Claim 5 (depends on 1) The semiconductor package according to claim 1, further comprising a first mask layer adjacent to the first conductive patterns and in contact with the first build-up layer, wherein from a top view, outer opening patterns of the first mask layer are larger than inner opening patterns of the first mask layer. ### Claim 6 (depends on 1) The semiconductor package according to claim 1, further comprising: a package structure, disposed over and electrically connected to the first redistribution layer structure; and second bonding elements, disposed between and electrically connected to the first redistribution layer structure and the package structure. ### Claim 7 (depends on 6) The semiconductor package according to claim 6, wherein a dimension of the first bonding elements is larger than a dimension of the second bonding elements. ### Claim 8 (depends on 6) The semiconductor package according to claim 6, wherein the package structure comprises package components and a second redistribution layer structure, and the second redistribution layer structure is disposed between and electrically connected to the package components and the second bonding elements. ### Claim 9 (depends on 1) The semiconductor package according to claim 1, wherein from a top view, each of the outer conductive patterns and the inner conductive patterns has an oval shape with a long axis towards the same direction, and the long axis of the oval shape is inclined with respect to an edge of the circuit board structure. ### Claim 10 A semiconductor package, comprising: a circuit board structure, comprising: first conductive patterns located on a surface of the circuit board structure; and a first mask layer located on the surface of the circuit board structure and aside the first conductive patterns; a first redistribution layer structure, disposed over the circuit board structure; first bonding elements bonded to the first conductive patterns and disposed between and electrically connected to the first redistribution layer structure and the circuit board structure, wherein an encapsulation layer is disposed between the first redistribution layer structure and the circuit board structure and located within at least some gaps between the first bonding elements and the first mask layer. ### Claim 11 (depends on 10) The semiconductor package according to claim 10, wherein dimensions of the first conductive patterns are substantially the same across the circuit board structure. ### Claim 12 (depends on 10) The semiconductor package according to claim 10, wherein dimensions of the first conductive patterns are varied across the circuit board structure. ### Claim 13 (depends on 12) The semiconductor package according to claim 12, wherein the first conductive patterns comprise inner conductive patterns and outer conductive patterns surrounding the inner conductive patterns, and a dimension of the inner conductive patterns is less than a dimension of the outer conductive patterns. ### Claim 14 (depends on 10) The semiconductor package according to claim 10, wherein from a top view, each of the first conductive patterns has an circular shape. ### Claim 15 (depends on 10) The semiconductor package according to claim 10, wherein from a top view, each of the first conductive patterns has an oval shape with a long axis towards the same direction. ### Claim 16 A method of manufacturing a semiconductor package, comprising: providing a circuit board structure, wherein the circuit board substrate comprises: a core layer and first and second build-up layers respectively located on two surfaces of the core layer; and-first conductive patterns located on the first build-up layer; forming a first redistribution layer structure over the circuit board structure; forming first bonding elements, wherein the first bonding elements are disposed on the first conductive patterns and located between and electrically connected to the first redistribution layer structure and the circuit board structure; and forming an encapsulation layer, wherein a portion of the encapsulation layer is disposed between the first redistribution layer structure and the circuit board structure and another portion of the encapsulation layer covers a sidewall of the circuit board structure, and cutting the first redistribution layer structure and the encapsulation layer, so that a sidewall of the first redistribution layer structure is flush with a sidewall of the encapsulation layer after the cutting process. ### Claim 17 (depends on 16) The method according to claim 16, wherein the first bonding elements cover sidewalls and tops of at least some of the outermost first conductive patterns after forming the first bonding elements. ### Claim 18 (depends on 16) The method according to claim 16, wherein air gaps are formed between at least some of the outermost first conductive patterns and the adjacent first opening patterns of the first mask layer after forming the first bonding elements. ### Claim 19 (depends on 16) The method according to claim 16, wherein the encapsulation layer is further formed between at least some of the outermost first conductive patterns and the adjacent first opening patterns of the first mask layer. ### Claim 20 (depends on 16) The method according to claim 16, further comprising: bonding a package structure to the first redistribution layer structure opposite to the circuit board structure.